Thin film sputtered silicon for silicon wafer bonding applications

The transfer of functional integrated circuit layers to other substrates is being investigated for smart-sensors, MEMS, 3-D ICs and mixed semiconductor circuits. There is a need for a planarisation and bondable layer which can be deposited at low temperature and which is IC compatible. This paper describes for the first time the successful use of sputtered silicon in this role for applications as outlined above where high temperature post bond anneals are not required. It also highlights the problems of using sputtered silicon as a bonding layer in applications where post bond temperatures greater than 400C are required.

Laser annealing of sputtered silicon for wafer-bonding applications

Sputtered silicon is investigated as a bonding layer for transfer of pre-processed silicon layers to various insulating substrates. Although the material appears suitable for low temperature processing, previous work has shown that gas trapped in the pores of the sputtered material is released at temperatures above 350 degrees C and further increases of temperature lead to destruction of any bonded interface. Pre-annealing at 1000 degrees C before bonding drives out gas and/or seals the surface, but for device applications where processing temperatures must be kept below about 300 degrees C, this technique cannot be used. In the current work, we have investigated the effect of excimer laser-annealing to heat the sputtered silicon surface to high temperature whilst minimising heating of the underlying substrate. Temperature profile simulations are presented and the results of RBS, TEM and AFM used to characterise the annealed layers. The results verify that gases are present in the sub-surface layers and suggest that while sealing of the surface is important for suppression of the out-diffusion of gases, immediate surface gas removal may also play a role. The laser-annealing technique appears to be an effective method of treating sputtered silicon, yielding a low roughness surface suitable for wafer bonding, thermal splitting and layer transfer.

Fabrication of Sub-micron Active Layer SSOI Substrates using Ion Splitting and Wafer Bonding Technologies

This paper reports the fabrication of SSOI (Silicon on Silicide On Insulator) substrates with active silicon regions only 0.5mum thick, incorporating LPCVD low resistivity tungsten silicide (WSix) as the buried layer. The substrates were produced using ion splitting and two stages of wafer bonding. Scanning acoustic microscope imaging confirmed that the bond interfaces are essentially void-free. These SSOI wafers are designed to be employed as substrates for mm-wave reflect-array diodes, and the required selective etch technology is described together with details of a suitable device.

Germanium on Sapphire By Wafer Bonding

This paper describes the creation of a germanium on sapphire platform, via wafer bonding technology, for system-on-a-chip applications. Similar thermal coefficients of expansion between germanium (5.8 x 10-6 K-1) and sapphire (5 x 10-6 K-1) make the bonding of germanium to sapphire a reality. Germanium directly bonded to sapphire results in microvoid generation during post bond annealing. Inclusion of an interface layer such as silicon dioxide layer by plasma enhanced chemical vapour deposition, prior to bonding, results in a microvoid free bond interface after annealing. Grinding and polishing of the subsequent germanium layer has been achieved leaving a thick germanium on sapphire (GeOS) substrate. Submicron GeOS layers have also been achieved with hydrogen/helium co-implantation and layer transfer. Circular geometry transistors exhibiting a field effect mobility of 890 cm2/V s have been fabricated onto the thick germanium on sapphire layer.

FAULT-TOLERANT ALGORITHM FOR HIGH-AVAILABILITY AND WAFER SCALE SYSTEMS.

In this paper, the authors have presented one approach to configuring a Wafer-Scale Integration Chip. The approach described is called the 'WINNER', in which bus channels and an external controller for configuring the working processors are not required. In addition, the technique is applicable to high availability systems constructed using conventional methods. The technique can also be extended to arrays of arbitrary size and with any degree of fault tolerance simply by using an appropriate number of cells.

Whole wafer magnetostriction metrology for magnetic films and multilayers

The requirements for metrology of magnetostriction in complex multilayers and on whole wafers present challenges. An elegant technique based on radius of curvature deformation of whole wafers in a commercial metrology tool is described. The method is based on the Villari effect through application of strain to a film by introducing a radius of curvature. Strain can be applied tensilely and compressively depending on the material. The design, while implemented on 3'' wafers, is scalable. The approach removes effects arising from any shape anisotropy that occurs with smaller samples, which can lead to a change in magnetic response. From the change in the magnetic anisotropy as a function of the radius, saturation magnetostriction ?s can be determined. Dependence on film composition and film thickness was studied to validate the radius of curvature approach with other techniques. ?s decreases from positive values to negative values through an increase in Ni concentration around the permalloy composition, and ?s also increases with a decrease in film thickness, in full agreement with previous reports. We extend the technique by demonstrating the technique applied to a multi-layered structure. These results verify the validity of the method and are an important step to facilitate further work in understanding how manipulation of multilayered films can offer tailored magnetostriction.