Compact Toffoli gate using weighted graph states

We introduce three compact graph states that can be used to perform a measurement-based Toffoli gate. Given a weighted graph of six, seven, or eight qubits, we show that success probabilities of 1/4, 1/2, and 1, respectively, can be achieved. Our study puts a measurement-based version of this important quantum logic gate within the reach of current experiments. As the graphs are setup independent, they could be realized in a variety of systems, including linear optics and ion traps.

Control-limited perfect state transfer, quantum stochastic resonance, and many-body entangling gate in imperfect qubit registers

We propose a protocol for perfect quantum state transfer that is resilient to a broad class of realistic experimental imperfections, including noise sources that could be modeled either as independent Markovian baths or as certain forms of spatially correlated environments. We highlight interesting connections between the fidelity of state transfer and quantum stochastic resonance effects. The scheme is flexible enough to act as an effective entangling gate for the generation of genuine multipartite entanglement in a control-limited setting. Possible experimental implementations using superconducting qubits are also briefly discussed.

Two Arginine-Glutamate Ionic Locks Near the Extracellular Surface of FFAR1 Gate Receptor Activation

Activation of a number of class A G protein-coupled receptors (GPCRs) is thought to involve two molecular switches, a rotamer toggle switch within the transmembrane domain and an ionic lock at the cytoplasmic surface of the receptor; however, the mechanism by which agonist binding changes these molecular interactions is not understood. Importantly, 80% of GPCRs including free fatty acid receptor 1 (FFAR1) lack the complement of amino acid residues implicated in either or both of these two switches; the mechanism of activation of these GPCRs is therefore less clear. By homology modeling, we identified two Glu residues (Glu-145 and Glu-172) in the second extracellular loop of FFAR1 that form putative interactions individually with two transmembrane Arg residues (Arg-183(5.39) and Arg-258(7.35)) to create two ionic locks. Molecular dynamics simulations showed that binding of agonists to FFAR1 leads to breakage of these Glu-Arg interactions. In mutagenesis experiments, breakage of these two putative interactions by substituting Ala for Glu-145 and Glu-172 caused constitutive receptor activation. Our results therefore reveal a molecular switch for receptor activation present on the extracellular surface of FFAR1 that is broken by agonist binding. Similar ionic locks between the transmembrane domains and the extracellular loops may constitute a mechanism common to other class A GPCRs also.

Low power field programmable gate array implementation of fast digital signal processing algorithms: characterisation and manipulation of data locality

Dynamic power consumption is very dependent on interconnect, so clever mapping of digital signal processing algorithms to parallelised realisations with data locality is vital. This is a particular problem for fast algorithm implementations where typically, designers will have sacrificed circuit structure for efficiency in software implementation. This study outlines an approach for reducing the dynamic power consumption of a class of fast algorithms by minimising the index space separation; this allows the generation of field programmable gate array (FPGA) implementations with reduced power consumption. It is shown how a 50% reduction in relative index space separation results in a measured power gain of 36 and 37% over a Cooley-Tukey Fast Fourier Transform (FFT)-based solution for both actual power measurements for a Xilinx Virtex-II FPGA implementation and circuit measurements for a Xilinx Virtex-5 implementation. The authors show the generality of the approach by applying it to a number of other fast algorithms namely the discrete cosine, the discrete Hartley and the Walsh-Hadamard transforms.

How crucial is back gate misalignment/oversize in double gate MOSFETs for ultra-low-voltage analog/rf applications?

In the present work, by investigating the influence of source/drain (S/D) extension region engineering (also known as gate-underlap architecture) in planar Double Gate (DG) SOI MOSFETs, we offer new design insights to achieve high tolerance to gate misalignment/oversize in nanoscale devices for ultra-low-voltage (ULV) analog/rf applications. Our results show that (i) misaligned gate-underlap devices perform significantly better than DC devices with abrupt source/drain junctions with identical misalignment, (ii) misaligned gate underlap performance (with S/D optimization) exceeds perfectly aligned DG devices with abrupt S/D regions and (iii) 25% back gate misalignment can be tolerated without any significant degradation in cut-off frequency (f(T)) and intrinsic voltage gain (A(VO)). Gate-underlap DG devices designed with spacer-to-straggle ratio lying within the range 2.5 to 3.0 show best tolerance to misaligned/oversize back gate and indeed are better than self-aligned DG MOSFETs with non-underlap (abrupt) S/D regions. Impact of gate length and silicon film thickness scaling is also discussed. These results are very significant as the tolerable limit of misaligned/oversized back gate is considerably extended and the stringent process control requirements to achieve self-alignment can be relaxed for nanoscale planar ULV DG MOSFETs operating in weak-inversion region. The present work provides new opportunities for realizing future ULV analog/rf design with nanoscale gate-underlap DG MOSFETs. (C) 2008 Elsevier Ltd. All rights reserved.