Modelling the behavior of solder joints for wafer level SiP

Design for manufacture of system-in-package (SiP) structures is dependent on a number of physical processes that affect the final quality of the package in terms of its performance and reliability. Solder joints are key structures in a SiP and their behavior can be the critical factor in terms of reliability. This paper discusses the results from a research programme on design for manufacturing of system in package (SiP) technologies. The focus of the paper is on thermo-mechanical modelling of solder joints. This includes the behavior of the joints during testing plus some important insights into the reflow process and how physical phenomena taking place at the assembly stage can affect solder joint behavior. Finite element analysis of a numerical model of an SiP structure with various design parameters is discussed. The goal of this analysis is to identify the most promising combination of design parameters which guarantee longer lifetime of the solder joints and hence the SiP component. The parameters that were studied are the size of the package (i.e. number of solder joints per row), the presence of the underfill and/or the reinforcement as well as the thickness of the passive die. Discussion was also provided on phenomena that take place during the reflow process where the solder joints are formed. In particular, the formation of intermetallics at the solder-pad interfaces

Design for reliability for wafer level system in package

This paper discusses the Design for Reliability modelling of several System-in-Package (SiP) structures developed by NXP and advanced on the basis of Wafer Level Packaging (WLP). Two different types of Wafer Level SiP (WLSiP) are presented and discussed. The main focus is on the modelling approach that has been adopted to investigate and analyse the board level reliability of the presented SiP configurations. Thermo-mechanical non-linear Finite Element Analysis (FEA) is used to analyse the effect of various package design parameters on the reliability of the structures and to identify design trends towards package optimisation. FEA is used also to gain knowledge on moulded wafer shrinkage and related issues during the wafer level fabrication. The paper provides a brief outline and demonstration of a design methodology for reliability driven design optimisation of SiP. The study emphasises the advantages of applying the methodology to address complex design problems where several requirements may exist and uncertainties and interactions between parameters in the design are common.

Thin film sputtered silicon for silicon wafer bonding applications

The transfer of functional integrated circuit layers to other substrates is being investigated for smart-sensors, MEMS, 3-D ICs and mixed semiconductor circuits. There is a need for a planarisation and bondable layer which can be deposited at low temperature and which is IC compatible. This paper describes for the first time the successful use of sputtered silicon in this role for applications as outlined above where high temperature post bond anneals are not required. It also highlights the problems of using sputtered silicon as a bonding layer in applications where post bond temperatures greater than 400C are required.

Laser annealing of sputtered silicon for wafer-bonding applications

Sputtered silicon is investigated as a bonding layer for transfer of pre-processed silicon layers to various insulating substrates. Although the material appears suitable for low temperature processing, previous work has shown that gas trapped in the pores of the sputtered material is released at temperatures above 350 degrees C and further increases of temperature lead to destruction of any bonded interface. Pre-annealing at 1000 degrees C before bonding drives out gas and/or seals the surface, but for device applications where processing temperatures must be kept below about 300 degrees C, this technique cannot be used. In the current work, we have investigated the effect of excimer laser-annealing to heat the sputtered silicon surface to high temperature whilst minimising heating of the underlying substrate. Temperature profile simulations are presented and the results of RBS, TEM and AFM used to characterise the annealed layers. The results verify that gases are present in the sub-surface layers and suggest that while sealing of the surface is important for suppression of the out-diffusion of gases, immediate surface gas removal may also play a role. The laser-annealing technique appears to be an effective method of treating sputtered silicon, yielding a low roughness surface suitable for wafer bonding, thermal splitting and layer transfer.

Fabrication of Sub-micron Active Layer SSOI Substrates using Ion Splitting and Wafer Bonding Technologies

This paper reports the fabrication of SSOI (Silicon on Silicide On Insulator) substrates with active silicon regions only 0.5mum thick, incorporating LPCVD low resistivity tungsten silicide (WSix) as the buried layer. The substrates were produced using ion splitting and two stages of wafer bonding. Scanning acoustic microscope imaging confirmed that the bond interfaces are essentially void-free. These SSOI wafers are designed to be employed as substrates for mm-wave reflect-array diodes, and the required selective etch technology is described together with details of a suitable device.

Germanium on Sapphire By Wafer Bonding

This paper describes the creation of a germanium on sapphire platform, via wafer bonding technology, for system-on-a-chip applications. Similar thermal coefficients of expansion between germanium (5.8 x 10-6 K-1) and sapphire (5 x 10-6 K-1) make the bonding of germanium to sapphire a reality. Germanium directly bonded to sapphire results in microvoid generation during post bond annealing. Inclusion of an interface layer such as silicon dioxide layer by plasma enhanced chemical vapour deposition, prior to bonding, results in a microvoid free bond interface after annealing. Grinding and polishing of the subsequent germanium layer has been achieved leaving a thick germanium on sapphire (GeOS) substrate. Submicron GeOS layers have also been achieved with hydrogen/helium co-implantation and layer transfer. Circular geometry transistors exhibiting a field effect mobility of 890 cm2/V s have been fabricated onto the thick germanium on sapphire layer.