From bit level systolic arrays to HDTV processor chips

The initial part of this paper reviews the early challenges (c 1980) in achieving real-time silicon implementations of DSP computations. In particular, it discusses research on application specific architectures, including bit level systolic circuits that led to important advances in achieving the DSP performance levels then required. These were many orders of magnitude greater than those achievable using programmable (including early DSP) processors, and were demonstrated through the design of commercial digital correlator and digital filter chips. As is discussed, an important challenge was the application of these concepts to recursive computations as occur, for example, in Infinite Impulse Response (IIR) filters. An important breakthrough was to show how fine grained pipelining can be used if arithmetic is performed most significant bit (msb) first. This can be achieved using redundant number systems, including carry-save arithmetic. This research and its practical benefits were again demonstrated through a number of novel IIR filter chip designs which at the time, exhibited performance much greater than previous solutions. The architectural insights gained coupled with the regular nature of many DSP and video processing computations also provided the foundation for new methods for the rapid design and synthesis of complex DSP System-on-Chip (SoC), Intellectual Property (IP) cores. This included the creation of a wide portfolio of commercial SoC video compression cores (MPEG2, MPEG4, H.264) for very high performance applications ranging from cell phones to High Definition TV (HDTV). The work provided the foundation for systematic methodologies, tools and design flows including high-level design optimizations based on "algorithmic engineering" and also led to the creation of the Abhainn tool environment for the design of complex heterogeneous DSP platforms comprising processors and multiple FPGAs. The paper concludes with a discussion of the problems faced by designers in developing complex DSP systems using current SoC technology. © 2007 Springer Science+Business Media, LLC.

High performance VLSI architecture for division and square root

A novel high performance bit parallel architecture to perform square root and division is proposed. Relevant VLSI design issues have been addressed. By employing redundant arithmetic and a semisystolic schedule, the throughput has been made independent of the size of the array.

VLSI module for high-performance multiply, square root and divide

A high-performance VLSI architecture to perform multiply-accumulate, division and square root operations is proposed. The circuit is highly regular, requires only minimal control and can be pipelined right down to the bit level. The system can also be reconfigured on every cycle to perform any one of these operations. The gate count per row has been estimated at (27n+70) gate equivalents where n is the divisor wordlength. The throughput rate, which equals the clock speed, is the same for each operation and is independent of the wordlength. This is achieved through the combination of pipelining and redundant arithmetic. With a 1.0 µm CMOS technology and extensive pipelining, throughput rates in excess of 70 million operations per second are expected.

Bit-Level systolic architectures for high performance IIR filtering

Several novel systolic architectures for implementing densely pipelined bit parallel IIR filter sections are presented. The fundamental problem of latency in the feedback loop is overcome by employing redundant arithmetic in combination with bit-level feedback, allowing a basic first-order section to achieve a wordlength-independent latency of only two clock cycles. This is extended to produce a building block from which higher order sections can be constructed. The architecture is then refined by combining the use of both conventional and redundant arithmetic, resulting in two new structures offering substantial hardware savings over the original design. In contrast to alternative techniques, bit-level pipelinability is achieved with no net cost in hardware. © 1989 Kluwer Academic Publishers.

SYSTOLIC IIR FILTERS WITH BIT LEVEL PIPELINING.

A novel bit-level systolic array architecture for implementing first-order IIR filter sections is presented. A latency of only two clock cycles is achieved by using a radix-4 redundant number representation, performing the recursive computation most-significant-digit first, and feeding back each digit of the result as soon as it is available.

Bit-level systolic architecture for very high performance IIR filters

A novel bit-level systolic array architecture for implementing bit-parallel IIR filter sections is presented. The authors have shown previously how the fundamental obstacle of pipeline latency in recursive structures can be overcome by the use of redundant arithmetic in combination with bit-level feedback. These ideas are extended by optimizing the degree of redundancy used in different parts of the circuit and combining redundant circuit techniques with those of conventional arithmetic. The resultant architecture offers significant improvements in hardware complexity and throughput rate.

VLSI processor for high-performance arithmetic computations

A high performance VLSI architecture to perform combined multiply-accumulate, divide, and square root operations is proposed. The circuit is highly regular, requires only minimal control, and can be pipelined right down to the bit level. The system can also be reconfigured on every cycle to perform one or more of these operations. The throughput rate for each operation is the same and is wordlength independent. This is achieved using redundant arithmetic. With current CMOS technology, throughput rates in excess of 80 million operations per second are expected.

Bit-level systolic arrays for IIR filtering.

A novel bit-level systolic array architecture for implementing IIR (infinite-impulse response) filter sections is presented. A first-order section achieves a latency of only two clock cycles by using a radix-2 redundant number representation, performing the recursive computation most significant digit first, and feeding back each digit of the result as soon as it is available. The design is extended to produce a building block from which second- and higher-order sections can be connected.

Programmable high-performance IIR filter chip

The paper presents a state-of-the-art commercial demonstrator chip for infinite impulse response (IIR) filtering. The programmable IIR filter chip contains eight multiplier/accumulators that can be configured in one of five different modes to implement up to a 16th-order IIR filter. The multiply-accumulate block is based on a highly regular systolic array architecture and uses a redundant number system to overcome problems of pipelining in the feedback loop. The chip has been designed using the GEC Plessey Semiconductors CLA 78000 series gate array, operates on 16-bit two's complement data and has a clock speed of 30 MHz. Issues such as overflow detection and design for testability have also been addressed and are described.

Assessing family members' satisfaction with information sharing and communication during Hospital care at the end of life

Context: Despite the fact that most deaths occur in hospital, problems remain with how patients and families experience care at the end of life when a death occurs in a hospital. Objectives: (1) assess family member satisfaction with information sharing and communication, and (2) examine how satisfaction with information sharing and communication is associated with patient factors. Methods: Using a cross-sectional survey, data were collected from family members of adult patients who died in an acute care organization. Correlation and factor analysis were conducted, and internal consistency assessed using Cronbach's alpha. Linear regression was performed to determine the relationship among patient variables and satisfaction on the Information Sharing and Communication (ISC) scale. Results: There were 529 questionnaires available for analysis. Following correlation analysis and the dropping of redundant and conceptually irrelevant items, seven items remained for factor analysis. One factor was identified, described as information sharing and communication, that explained 76.3% of the variance. The questionnaire demonstrated good content and reliability (Cronbach's alpha 0.96). Overall, family members were satisfied with information sharing and communication (mean total satisfaction score 3.9, SD 1.1). The ISC total score was significantly associated with patient gender, the number of days in hospital before death, and the hospital program where the patient died. Conclusions: The ISC scale demonstrated good content validity and reliability. The ISC scale offers acute care organizations a means to assess the quality of information sharing and communication that transpires in care at the end of life. © Copyright 2013, Mary Ann Liebert, Inc.

Inference and Declaration of Independence in Task-Parallel Programs

The inherent difficulty of thread-based shared-memory programming has recently motivated research in high-level, task-parallel programming models. Recent advances of Task-Parallel models add implicit synchronization, where the system automatically detects and satisfies data dependencies among spawned tasks. However, dynamic dependence analysis incurs significant runtime overheads, because the runtime must track task resources and use this information to schedule tasks while avoiding conflicts and races.
We present SCOOP, a compiler that effectively integrates static and dynamic analysis in code generation. SCOOP combines context-sensitive points-to, control-flow, escape, and effect analyses to remove redundant dependence checks at runtime. Our static analysis can work in combination with existing dynamic analyses and task-parallel runtimes that use annotations to specify tasks and their memory footprints. We use our static dependence analysis to detect non-conflicting tasks and an existing dynamic analysis to handle the remaining dependencies. We evaluate the resulting hybrid dependence analysis on a set of task-parallel programs.

An intelligent configuration-sampling based local motion planner for robotic manipulators

Manipulator motion planning is a task which relies heavily on the construction of a configuration space prior to path planning. However when fast real-time motion is needed, the full construction of the manipulator's high-dimensional configu-ration space can be too slow and expensive. Alternative planning methods, which avoid this full construction of the manipulator's configuration space are needed to solve this problem. Here, one such existing local planning method for manipulators based on configuration-sampling and subgoal-selection has been extended. Using a modified Artificial Potential Fields (APF) function, goal-configuration sampling and a novel subgoal selection method, it provides faster, more optimal paths than the previously proposed work. Simulation results show a decrease in both runtime and path lengths, along with a decrease in unexpected local minimum and crashing issues.

The combined effects of diabetes and ionising radiation on the rat retina: an ultrastructural study

The combined effect of STZ-diabetes and ionising radiation on the rat retina was investigated. Wistar rats, which had been diabetic for 6 months, were irradiated with a single dose of x-rays (1500 cGy) and the ultrastructural effects evaluated at 4-10 mths post-irradiation. At 4 months post-irradiation, the outer nuclear layer of the retina was greatly reduced in thickness and the photoreceptor outer segments were disorganised and reduced in length. In addition, the nerve fibre layer contained many cytoid bodies and there were many redundant basement membrane tubes throughout the inner retina. By 6 months post-irradiation, the photoreceptor cells were virtually absent, bringing the external limiting membrane into close apposition to the RPE. Throughout large areas of the outer retina, RPE cells were hypertrophic and some had proliferated into the inner retina. In many regions, proliferating retinal capillaries were observed within the RPE layer, and at 8 months post-irradiation, some vessels extended into the inner retina accompanied by RPE cells. At 10 months post-irradiation, the RPE was atrophic and degenerative with retinal glial cells coming into contact with Bruch's membrane. In some areas, the glia which had breached Bruch's membrane had invaded the underlying choroid. Where glial cells contacted the choriocapillaries, the vessels assumed the appearance of retinal vessels with plump endothelia and no fenestrations. This study has described a progressive inner retinal ischemia, with cytoid bodies, capillary non-perfusion and general atrophy of the inner retina intensifying markedly with increasing post-irradiation time.(ABSTRACT TRUNCATED AT 250 WORDS)

Self-Feedback Motion Control for Cable-Driven Parallel Manipulators

This article proposes a closed-loop control scheme based on joint-angle feedback for cable-driven parallel manipulators (CDPMs), which is able to overcome various difficulties resulting from the flexible nature of the driven cables to achieve higher control accuracy. By introducing a unique structure design that accommodates built-in encoders in passive joints, the seven degrees of freedom (7-DOF) CDPM can obtain joint angle values without external sensing devices, and it is used for feedback control together with a proper closed-loop control algorithm. The control algorithm has been derived from the time differential of the kinematic formulation, which relates the joint angular velocities to the time derivative of cable lengths. In addition, the Lyapunov stability theory and Monte Carlo method have been used to mathematically verify the self-feedback control law that has tolerance for parameter errors. With the aid of co-simulation technique, the self-feedback closed-loop control is applied on a 7-DOF CDPM and it shows higher motion accuracy than the one with an open-loop control. The trajectory tracking experiment on the motion control of the 7-DOF CDPM demonstrated a good performance of the self-feedback control method.