SYSTOLIC IIR FILTERS WITH BIT LEVEL PIPELINING.
| Data(s) |
01/01/1988
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|---|---|
| Resumo |
A novel bit-level systolic array architecture for implementing first-order IIR filter sections is presented. A latency of only two clock cycles is achieved by using a radix-4 redundant number representation, performing the recursive computation most-significant-digit first, and feeding back each digit of the result as soon as it is available. |
| Identificador | |
| Idioma(s) |
eng |
| Direitos |
info:eu-repo/semantics/restrictedAccess |
| Fonte |
Woods , R F , Knowles , S C , McCanny , J V & McWhirter , J G 1988 , ' SYSTOLIC IIR FILTERS WITH BIT LEVEL PIPELINING. ' ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings , pp. 2072-2075 . |
| Tipo |
article |
