High performance VLSI architecture for division and square root

Autoria(s): McQuillan, S.E.; McCanny, J.V.; Woods, R.F.
Data(s)

01/01/1991
Resumo

A novel high performance bit parallel architecture to perform square root and division is proposed. Relevant VLSI design issues have been addressed. By employing redundant arithmetic and a semisystolic schedule, the throughput has been made independent of the size of the array.
Identificador

http://pure.qub.ac.uk/portal/en/publications/high-performance-vlsi-architecture-for-division-and-square-root(0b825076-0819-42cc-9d1a-b5a389ae9547).html

http://www.scopus.com/inward/record.url?partnerID=yv4JPVwI&eid=2-s2.0-0025855509&md5=8bd6bcaab5f9f53d59b55304b7d3ced2
Idioma(s)

eng
Direitos

info:eu-repo/semantics/restrictedAccess
Fonte

McQuillan , S E , McCanny , J V & Woods , R F 1991 , ' High performance VLSI architecture for division and square root ' Electronics Letters , vol 27 , no. 1 , pp. 20-21 .
Tipo

article
Acesso ao item digital