Programmable high-performance IIR filter chip
Data(s) |
01/06/1995
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Resumo |
The paper presents a state-of-the-art commercial demonstrator chip for infinite impulse response (IIR) filtering. The programmable IIR filter chip contains eight multiplier/accumulators that can be configured in one of five different modes to implement up to a 16th-order IIR filter. The multiply-accumulate block is based on a highly regular systolic array architecture and uses a redundant number system to overcome problems of pipelining in the feedback loop. The chip has been designed using the GEC Plessey Semiconductors CLA 78000 series gate array, operates on 16-bit two's complement data and has a clock speed of 30 MHz. Issues such as overflow detection and design for testability have also been addressed and are described. |
Identificador | |
Idioma(s) |
eng |
Direitos |
info:eu-repo/semantics/restrictedAccess |
Fonte |
Woods , R F , Floyd , G , Wood , K , Evans , R & McCanny , J V 1995 , ' Programmable high-performance IIR filter chip ' IEE Proceedings - Circuits, Devices and Systems , vol 142 , no. 3 , pp. 179-185 . DOI: 10.1049/ip-cds:19951892 |
Tipo |
article |