Constructing The Ethos of Tolerance and Respect in an Integrated School: The role of Teachers

This article seeks to explore how teachers develop tolerance and respect within an inclusive school
in Northern Ireland. Drawing on interviews and observation of 18 teachers, it will be shown that
teachers’ own personal values and assumptions exert a defining influence on the school ethos. It will
be argued that if teachers are not accorded the time and space to develop an understanding
of their own values and beliefs then there is the potential for schools to simply reinforce the psychological
barriers which sustain division.

What price harmony? Teachers' methods of delivering an ethos of tolerance and respect for diversity in an integrated school in Northern Ireland

The aim of the paper is to explore teachers’ methods of delivering an ethos of tolerance, respect
and mutual understanding in one integrated secondary school in Northern Ireland. Drawing on
interviews with teachers in the school, it is argued that most teachers make ‘critical choices’
which both reflect and reinforce a ‘culture of avoidance’, whereby politically or religiously contentious
issues are avoided rather than explored. Although teachers are well-intentioned in making
these choices, it is shown that they have the potential to create the conditions that maintain or even
harden psychological boundaries between Catholics and Protestants rather than dilute them.

Electrical Characterisation of SOI Substrates Incorporating WSix Ground Planes

Silicon-on-insulator (SOI) substrates incorporating tungsten silicide ground planes (GPs) have been shown to offer the lowest reported crosstalk figure of merit for application in mixed signal integrated circuits. The inclusion of the silicide layer in the structure may lead to stress or defects in the overlying SOI layers and resultant degradation of device performance. It is therefore essential to establish the quality of the silicon on the GPSOI substrate. MOS capacitor structures have been employed in this paper to characterize these GPSOI substrates for the first time. High quality MOS capacitor characteristics have been achieved with minority carrier lifetime of similar to 0.8 ms. These results show that the substrate is suitable for device manufacture with no degradation in the silicon due to stress or metallic contamination resulting from the inclusion of the underlying silicide layer.

Parameter sensitivity for optimal design of 65 nm node SOI transistors

Mixed-mode simulation, where device simulation is embedded directly within a circuit simulator, is used for the first time to provide scaling guidelines to achieve optimal digital circuit performance for double gate SOI MOSFETs. This significant advance overcomes the lack of availability of SPICE model parameters. The sensitivity of the gate delay and on-off current ratio to each of the key geometric and technological parameters of the transistor is quantified. The impact of the source-drain doping profile on circuit performance is comprehensively investigated.

Optimisation of source/drain extension region profile for suppression of short channel effects in sub-50 nm DG SOI MOSFETs with high- k gate dielectrics

Novel technology dependent scaling parameters i.e. spacer to gradient ratio and effective channel length (Leff) are proposed for source/drain engineered DG MOSFET, and their significance in minimizing short channel effects (SCES) in high-k gate dielectrics is discussed in detail. Results show that a high-k dielectric should be associated with a higher spacer to gradient ratio to minimise SCEs The analytical model agrees with simulated data over the entire range of spacer widths, doping gradients, high-k gate dielectrics and effective channel lengths.

Ultralow Silicon Substrate Noise Crosstalk Using Metal Faraday Cages in an SOI Technology

In mixed signal integrated circuits noise from the digital circuitry can upset the sensitive analogue circuitry. The Faraday cage structure reported here is based on the unique ground plane SOI technology developed some of the authors. The suppression of crosstalk achieved is an order of magnitude greater than that previously published for frequencies up to 10 GHz. The significance of the technology will be even greater as the operating frequency is increased. This collaborative EPSRC project was judge as tending to outstanding.

SiGe HBTs on Bonded SOI Incorporating Buried Silicide Layers

The performance of silicon bipolar transistors has been significantly improved by the use of ultra narrow base layers of SiGe. To further improve device performance by minimising parasitic resistance and capacitance the authors produced an unique silicon-on-insulator (SOI) substrate incorporating a buried tungsten disilicide layer. This structure forms the basis of a recent submission by Zarlink Semiconductors ( Silvaco, DeMontfort & Queen�s) to DTI for high voltage devices for automotive applications. The Queen�s part of the original EPSRC project was rated as tending to outstanding.

The general and specific effects of educational programmes aimed at promoting awareness of and respect for diversity among young children

This article reports the findings of a mixed-method evaluation of a pilot educational programme undertaken with 6-7 year olds in a sample of primary schools in England with the aim of increasing their awareness of and respect for diversity through theatre, workshops and related teacher-led classroom activities. The qualitative feedback from the teachers involved was extremely positive and encouraging and an analysis of the actual impact of the pilot programme on the children’s attitudes and awareness, using an experimental design, demonstrated some positive effects. In particular, the programme was found to increase the children’s general awareness of diversity and their ability to recognise instances of exclusion. While not a planned objective of the pilot programme, the evaluation also examined whether it had any effects on the children’s attitudes to specific differences, in this particular case racial differences. Interestingly, however, no evidence was found of any change in the children’s racial attitudes. With this in mind the article suggests that there is a need to distinguish between the general and specific effects of such educational programmes. The article considers the implications of this for future work in the area and also stresses the need to undertake more thorough and rigorous evaluations of such initiatives.

Optimisation of trench isolated bipolar transistors on SOI substrates by 3D electro-thermal simulations

This paper provides a comprehensive analysis of thermal resistance of trench isolated bipolar transistors on SOI substrates based on 3D electro-thermal simulations calibrated to experimental data. The impact of emitter length, width, spacing and number of emitter fingers on thermal resistance is analysed in detail. The results are used to design and optimise transistors with minimum thermal resistance and minimum transistor area. (c) 2007 Elsevier Ltd. All rights reserved.

6-T SRAM cell design with nanoscale double-gate SOI MOSFETs: impact of source/drain engineering and circuit topology

The impact of source/drain engineering on the performance of a six-transistor (6-T) static random access memory (SRAM) cell, based on 22 nm double-gate (DG) SOI MOSFETs, has been analyzed using mixed-mode simulation, for three different circuit topologies for low voltage operation. The trade-offs associated with the various conflicting requirements relating to read/write/standby operations have been evaluated comprehensively in terms of eight performance metrics, namely retention noise margin, static noise margin, static voltage/current noise margin, write-ability current, write trip voltage/current and leakage current. Optimal design parameters with gate-underlap architecture have been identified to enhance the overall SRAM performance, and the influence of parasitic source/drain resistance and supply voltage scaling has been investigated. A gate-underlap device designed with a spacer-to-straggle (s/sigma) ratio in the range 2-3 yields improved SRAM performance metrics, regardless of circuit topology. An optimal two word-line double-gate SOI 6-T SRAM cell design exhibits a high SNM similar to 162 mV, I-wr similar to 35 mu A and low I-leak similar to 70 pA at V-DD = 0.6 V, while maintaining SNM similar to 30% V-DD over the supply voltage (V-DD) range of 0.4-0.9 V.

Performance projections and design optimization of planar double gate SOI MOSFETs for logic technology applications

In this paper, by investigating the influence of source/drain extension region engineering (also known as gate-source/drain underlap) in nanoscale planar double gate (DG) SOI MOSFETs, we offer new insights into the design of future nanoscale gate-underlap DG devices to achieve ITRS projections for high performance (HP), low standby power (LSTP) and low operating power (LOP) logic technologies. The impact of high-kappa gate dielectric, silicon film thickness, together with parameters associated with the lateral source/drain doping profile, is investigated in detail. The results show that spacer width along with lateral straggle can not only effectively control short-channel effects, thus presenting low off-current in a gate underlap device, but can also be optimized to achieve lower intrinsic delay and higher on-off current ratio (I-on/I-off). Based on the investigation of on-current (I-on), off-current (I-off), I-on/I-off, intrinsic delay (tau), energy delay product and static power dissipation, we present design guidelines to select key device parameters to achieve ITRS projections. Using nominal gate lengths for different technologies, as recommended from ITRS specification, optimally designed gate-underlap DG MOSFETs with a spacer-to-straggle (s/sigma) ratio of 2.3 for HP/LOP and 3.2 for LSTP logic technologies will meet ITRS projection. However, a relatively narrow range of lateral straggle lying between 7 to 8 nm is recommended. A sensitivity analysis of intrinsic delay, on-current and off-current to important parameters allows a comparative analysis of the various design options and shows that gate workfunction appears to be the most crucial parameter in the design of DG devices for all three technologies. The impact of back gate misalignment on I-on, I-off and tau is also investigated for optimized underlap devices.