Ultralow Silicon Substrate Noise Crosstalk Using Metal Faraday Cages in an SOI Technology


Autoria(s): Stefanou, S.; Hamel, J.S.; Baine, Paul; Bain, Michael; Armstrong, Mervyn; Gamble, Harold; Kraft, M.; Kemhadjian, H.A.
Data(s)

01/03/2004

Resumo

In mixed signal integrated circuits noise from the digital circuitry can upset the sensitive analogue circuitry. The Faraday cage structure reported here is based on the unique ground plane SOI technology developed some of the authors. The suppression of crosstalk achieved is an order of magnitude greater than that previously published for frequencies up to 10 GHz. The significance of the technology will be even greater as the operating frequency is increased. This collaborative EPSRC project was judge as tending to outstanding.

Identificador

http://pure.qub.ac.uk/portal/en/publications/ultralow-silicon-substrate-noise-crosstalk-using-metal-faraday-cages-in-an-soi-technology(cc0e5aff-0ebb-45f6-8863-eed3dc2ed11d).html

http://dx.doi.org/10.1109/TED.2003.822348

http://www.scopus.com/inward/record.url?scp=1642306308&partnerID=8YFLogxK

Idioma(s)

eng

Direitos

info:eu-repo/semantics/restrictedAccess

Fonte

Stefanou , S , Hamel , J S , Baine , P , Bain , M , Armstrong , M , Gamble , H , Kraft , M & Kemhadjian , H A 2004 , ' Ultralow Silicon Substrate Noise Crosstalk Using Metal Faraday Cages in an SOI Technology ' IEEE Transactions on Electron Devices , vol 51(3) , no. 3 , pp. 486-491 . DOI: 10.1109/TED.2003.822348

Palavras-Chave #/dk/atira/pure/subjectarea/asjc/2200/2208 #Electrical and Electronic Engineering #/dk/atira/pure/subjectarea/asjc/3100/3101 #Physics and Astronomy (miscellaneous)
Tipo

article