What are you looking at?: Prisoner Confrontations and the Search for Respect

This article examines the occurrence of fights, assaults, arguments and threats of violence between adult male prisoners in an English category C prison. The self-narratives of 40 men are analysed to investigate whether some prisoners engage in more confrontations than others due to a psychological need to protect their identity. The findings indicate that how an individual understands and constructs their self-narrative can influence their involvement in aggressive behaviour. Implications for interventions attempting to reduce aggression are explored.

Reconsidering Respect: Its Role in the British Prison Service

This article examines the meaning of respect in the interpersonal relationships within Her Majesty’s Prison Service. It is argued that respect-as-esteem and respect-asconsideration are often confused and unequally emphasised in modern society. This confusion is especially evident within the prison context where, due to the prison service’s ‘decency agenda’, the respectful treatment of inmates has become a topical issue. What does respect mean in prison? Why is it important? How can respectful relationships be established between staff and inmates? This article discusses these questions and proposes that there are different forms of respect possible between people. It is argued that there needs to be a recognition of the nuances of meaning when we use the word respect and that ‘respect-as-consideration’ may be the form of respect most consistently achievable, at the present time, within interpersonal relationships in English and Welsh prisons.

Impact of gate-source/drain channel architecture on the performance of an operational transconductance amplifier (OTA)

In this work, we report on the significance of gate-source/drain extension region (also known as underlap design) optimization in double gate (DG) FETs to improve the performance of an operational transconductance amplifier (OTA). It is demonstrated that high values of intrinsic voltage gain (A(VO_OTA)) > 55 dB and unity gain frequency (f(T_OTA)) similar to 57 GHz in a folded cascode OTA can be achieved with gate-underlap channel design in 60 nm DG MOSFETs. These values correspond to 15 dB improvement in A(VO_OTA) and three fold enhancement in f(T_OTA) over a conventional non-underlap design. OTA performance based on underlap single gate SOI MOSFETs realized in ultra-thin body (UTB) and ultra-thin body BOX (UTBB) technologies is also evaluated. A(VO_OTA) values exhibited by a DG MOSFET-based OTA are 1.3-1.6 times higher as compared to a conventional UTB/UTBB single gate OTA. f(T_OTA) values for DG OTA are 10 GHz higher for UTB OTAs whereas a twofold improvement is observed with respect to UTBB OTAs. The simultaneous improvement in A(VO_OTA) and f(T_OTA) highlights the usefulness of underlap channel architecture in improving gain-bandwidth trade-off in analog circuit design. Underlap channel OTAs demonstrate high degree of tolerance to misalignment/oversize between front and back gates without compromising the performance, thus relaxing crucial process/technology-dependent parameters to achieve 'idealized' DG MOSFETs. Results show that underlap OTAs designed with a spacer-to-straggle (s/sigma) ratio of 3.2 and operated below a bias current (IBIAS) of 80 mu A demonstrate optimum performance. The present work provides new opportunities for realizing future ultra-wide band OTA design with underlap DG MOSFETs.

Fabrication and characterisation of high resistivity SOI substrates for monolithic high energy physics detectors

Silicon on Insulator (SOI) substrates offer a promising platform for monolithic high energy physics detectors with integrated read-out electronics and pixel diodes. This paper describes the fabrication and characterisation of specially-configured SOI substrates using improved bonded wafer ion split and grind/polish technologies. The crucial interface between the high resistivity handle silicon and the SOI buried oxide has been characterised using both pixel diodes and circular geometry MOS transistors. Pixel diode breakdown voltages were typically greater than 100V and average leakage current densities at 70 V were only 55 nA/ sq cm. MOS transistors subjected to 24 GeV proton irradiation showed an increased SOI buried oxide trapped charge of only 3.45x1011cn-2 for a dose of 2.7Mrad