新型硅基双异质外延SOI材料Si/γ-Al_2O_3/Si制备

异质外延法是目前制备新型SOI材料的技术途径之一。采用低压化学气相沉积技术(LPCVD)在硅衬底上先外延r-A1-2O-3绝缘单晶薄膜，制备出硅衬底上外延氧化物外延结构r-Al-2O-3／Si(EOS)，然后采用类似SOS薄膜生长的常压CVD(APCVD)方法在EOS上外延硅单晶薄膜，形成新型硅基双异质SOl材料Si／r-Al-2O-3／Si。利用反射高能电子衍射(RHEED)、X射线衍射(XRD)、俄歇电子能谱(AES)及MOS电学测量等技术表征分析了Si(100)／r-Al-2O-3(100)／Si(100)SOI异质结构的晶体结构、组分和电学性能。测试结果表明，已成功实现了高质量的新型双异质外延SOI结构材料Si(100)／ r-Al-2O-3(100)／Si(100)，r-Al-2O-3与Si外延薄膜均为单晶，r-Al-2O-3薄膜具有良好绝缘性能，SOI结构界面清晰陡峭，该SOI材料可应用于CMOS电路的研制。

16信道0．35μmCMOS／VCSEL光发射模块

研究了垂直腔面发射激光器（VCSEL）及其列阵器件的光谱特性、调制特性、高频特性及与微电子电路的兼容性，将1×16的VCSEL与CMOS专用集成电路进行多芯片组装（MCM），混合集成为16信道VCSEL光发射功能模块。测试过程中，功能模块的光电特性及其均匀性良好，测量的-3dB频带芝宽度大于2GHz。

倒装焊组装的光电混合集成RCE探测器面阵

报道了一种可用于并行光传输系统的64 * 64光探测器面阵。器件结构采用谐振腔增强型（RCE），吸收区由3层InGaAs/GaAs量子阱构成，谐振腔是由2组多层布拉格反射镜组成，工作波长位于980 nm。该器件利用倒装焊技术，将GaAs基的谐振腔增强型光探测器面阵与相应的Si基标准CMOS集成电路混合集成在一起，形成具备64 * 64路光并行接收及处理的大规模光电集成探测器面阵器件，并对光探测器面阵的主要特性进行了测试，测试结构显示该面阵具有均匀的电特性，反向偏压均大于14 V，暗电流约为10 nA数量级。

微光电子集成灵巧象素器件

采用MBE生长出大周期GaAs/AlGaAs多量子阱外延材料，研制了适用于倒装焊结构的自电光效应器件列阵，并与Si CMOS电路通过倒装焊工艺集成为微光电子集成灵巧象素器件。通过对光电特性测试表明，器件具有良好的光探测和光调制性能。

薄层SOS薄膜材料外延生长及其器件应用(英文)

亚微米CMOS/SOS器件发展对高质量的100--200纳米厚度的薄层SOS薄膜提出了更高的要求。实验证实：采用CVD方法生长的原生SOS薄膜的晶体质量可以通过固相外延工艺得到明显改进。该工艺包括：硅离子自注入和热退火。X射线双晶衍射和器件电学测量表明：多晶化的SOS薄膜固相外延生长导致硅外延层晶体质量改进和载流子迁移率提高。固相外延改进的薄层SOS薄膜材料能够应用于先进的CMOS电路。

SOI集成光电子器件

Silicon-on-insulator (SOI)集成光电子器件的工艺与标准CMOS工艺完全兼容，采用SOI技术可以实现低成本的整片集成光电子回路。文章回顾了近几年来SOI集成光电子器件的发展以及一些最新的研究进展。

A novel high sensitivity CE-PTHPT for optical fiber communication

Planar punch through heterojunction phototransistors with a novel emitter control electrode and ion- implanted isolation (CE-PTHPT) are investigated. The phototransistors have a working voltage of 3-10V and high sensitivity at low input power. The base of the transistor is completely depleted under operating condition. Base current is zero. The CE-PTHPT has an increased speed and a decreased noise. The novel CE-PTHPT has been fabricated in this paper. The optical gain of GaAlAs/GaAs CE-PTHPT for the incident light power 1.3 and 43nw with the wavelength of 0.8 mu m reached 1260 and 8108. The input noise current calculated is 5.46 x 10(-16) A/H-z(1/2). For polysilicon emitter CE-PTHPT, the optical gain is 3083 at the input power of 0.174 mu w. The optical gain of InGaAs/InP CE-PTHPT reaches 350 for an incident power of 0.3 mu w at the wavelength of 1.55 mu m. The CE-PTHPT detectors is promising as photo detectors for optical fiber communication system.

Scan test in 18x8 bits Booth Coding-Wallace Tree multiplier

Scan test can be inserted around hard IP cores that have not been designed with DFT approaches. An 18x18 bits Booth Coding-Wallace Tree multiplier has been designed with full custom approach with 0.61 m CMOS technology. When we reuse the multiplier in another chip, scan chain has been inserted around it to increase the fault coverage. After scan insertion, the multiplier needs 4.7% more areas and 24.4% more delay time, while the fault coverage reaches to 95%.

VCSEL based optoelectronic multiple chip modules

We report on optoelectronic multiple chip modules, consisting of vertical cavity surface emitting laser(VCSEL), photodetector and 1.2 mum CMOS electronic circuit, The hybrid integrated components operate at a date rate of 155Mb/s, which could be used in optical interconnects for multiple computers.

Multiple quantum well self electro-optic effect devices for optoelectronic smart pixels

The investigations on GaAs/AlGaAs multiple quantum well self electro-optic effect device (SEED) arrays for optoelectronic smart pixels are reported. The hybrid integration of GaAs/AlGaAs multiple quantum well devices flip-chip bonding directly over 1 mu m silicon CMOS circuits are demonstrated. The GaAs/AlGaAs multiple quantum well devices are designed for 850nm operation. The measurement results under applied biases show the good optoelectronic characteristics of elements in SEED arrays. The 4x4 optoelectronic crossbar structure consisting of hybrid CMOS-SEED smart pixels have been designed, which could be potentially used in optical interconnects for multiple processors.

Design of high brightness cubic-GaN LEDs grown on GaAs substrate

The Principle of optical thin film was used to calculate the feasibility of improving the light extraction efficiency of GaN/GaAs optical devices by wafer-bonding technique. The calculated results show that the light extraction efficiency of bonded samples can be improved by 2.66 times than the as-grown GaN/GaAs samples when a thin Ni layer was used as adhesive layer and Ag layer as reflective layer. Full reflectance spectrum comparison shows that reflectivity for the incident light of 459.2 nm of the bonded samples was improved by 2.4 times than the as-grown samples, which is consistent with the calculated results.

High-quality metamorphic HEMT grown on GaAs substrates by MBE

Metamorphic high electron mobility transistor (M-HEMT) structures have been grown on GaAs substrates by molecular beam epitaxy (MBE). Linearly graded and the step-graded InGaAs and InAlAs buffet layers hal e been compared, and TEM, PL and low-temperature Hall have been used to analyze the properties of the buffer layers and the M-HEMT structure. For a single-delta-doped M-HEMT structure with an In0.53Ga0.47As channel layer and a 0.8 mum step-graded InAlAs buffer layer, room-temperature mobility of 9000 cm(2)/V s and a sheet electron density as high as 3.6 x 10(12)/cm(2) are obtained. These results are nearly equivalent to those obtained for the same structure grown on an InP substrate. A basic M-HEMT device with 1 mum gate was fabricated, and g(m) is larger than 400 mS/mm. (C) 2001 Elsevier Science B.V. All rights reserved.

Improvement of thin silicon on sapphire (SOS) film materials and device performances by solid phase epitaxy

The increased emphasis on sub-micron CMOS/SOS devices has placed a demand for high quality thin silicon on sapphire (SOS) films with thickness of the order 100-200 nm. It is demonstrated that the crystalline quality of as-grown thin SOS films by the CVD method can be greatly improved by solid phase epitaxy (SPE) process: implantation of self-silicon ions and subsequent thermal annealing. Subsequent regrowth of this amorphous layer leads to a greater improvement in silicon layer crystallinity and channel carrier mobility, evidenced, respectively, by double crystal X-ray diffraction and electrical measurements. We concluded that the thin SPE SOS films are suitable for application to high-performance CMOS circuitry. (C) 2000 Elsevier Science S.A. All rights reserved.

Si-based optoelectronic devices and their attractive applications

The semiconductor photonics and optoelectronics which have a great significance in the development of advanced high technology of information systems will be discussed in this paper. The emphasis will be put on the recent research carried out in our laboratory in enhanced luminescence from low dimensional materials such as SiGe/Si and Er-doped Si-rich SiO2/Si and Er-doped SixNy/Si. A ring shape waveguide structure, used to promote the effective absorption coefficient in PIN photodetector for 1.3 mu m wavelength and a resonant cavity enhanced structure, used to improve the quantum efficiency and response in heterostructure photo-transistor (HPT), are also proposed in this paper.