OPTIMISED BIT LEVEL SYSTOLIC ARRAY FOR CONVOLUTION.

A bit level systolic array for computing the convolution operation is described. The circuit in question is highly regular and ideally suited to VLSI chip design. It is also optimized in the sense that all the cells contribute to the computation on each clock cycle. This makes the array almost four times more efficient than one which was previously described.

SOME SYSTOLIC ARRAY DEVELOPMENTS IN THE UNITED KINGDOM.

Two major UK systolic array projects are described. The first concerns the development of a wavefront array processor for adaptive beamforming; the second concerns the design of bit-level systolic arrays for high-performance signal processing.

USE OF UNIDIRECTIONAL DATA FLOW IN BIT-LEVEL SYSTOLIC ARRAY CHIPS.

We show how the architecture of two recently reported bit-level systolic array circuits - a single-bit coefficient correlator and a multibit convolver - may be modified to incorporate unidirectional data flow. This feature has advantages in terms of chip cascadability, fault tolerance and possible wafer-scale integration.

COMPLETELY ITERATIVE, PIPELINED MULTIPLIER ARRAY SUITABLE FOR VLSI.

A pipelined array multiplier which has been derived by applying 'systolic array' principles at the bit level is described. Attention is focused on a circuit which is used to multiply streams of parallel unsigned data. Then an algorithm is given which demonstrates that, with only a simple modification to the basic cell, the same array can cope with two's complement numbers. The resulting structure has a number of features whch make it attractive to LSI and VLSI. These include regularity and modularity.

BIT-LEVEL SYSTOLIC ARRAY CIRCUIT FOR MATRIX VECTOR MULTIPLICATION.

A bit-level systolic array for computing matrix x vector products is described. The operation is carried out on bit parallel input data words and the basic circuit takes the form of a 1-bit slice. Several bit-slice components must be connected together to form the final result, and authors outline two different ways in which this can be done. The basic array also has considerable potential as a stand-alone device, and its use in computing the Walsh-Hadamard transform and discrete Fourier transform operations is briefly discussed.

Automated design of DSP array processor chips

Details are presented of the DAC (DSP ASIC Compiler) silicon compiler framework. DAC allows a non-specialist to automatically design DSP ASICs and DSP ASIC cores directly form a high level specification. Typical designs take only several minutes and the resulting layouts are comparable in area and performance to handcrafted designs.

MULTIBIT CONVOLUTION USING A BIT LEVEL SYSTOLIC ARRAY.

A novel design for multibit convolver circuits is described. The circuits take the form of systolic arrays of simple one-bit processor and memory cells, with the result that they can operate at very high data rates and should be easy to implement using VLSI technology. An efficient method for handling two's complement data within the array is described and the relative advantages of this convolver design compared with more conventional circuits is discussed.

Systolic array system for vector quantization using transformed sub-band coding.

The use of bit-level systolic arrays in the design of a vector quantized transformed subband coding system for speech signals is described. It is shown how the major components of this system can be decomposed into a small number of highly regular building blocks that interface directly to one another. These include circuits for the computation of the discrete cosine transform, the inverse discrete cosine transform, and vector quantization codebook search.

Bit-level systolic array implementation of the Winograd Fourier transform algorithm

A bit level systolic array system is proposed for the Winograd Fourier transform algorithm. The design uses bit-serial arithmetic and, in common with other systolic arrays, features nearest-neighbor interconnections, regularity and high throughput. The short interconnections in this method contrast favorably with the long interconnections between butterflies required in the FFT. The structure is well suited to VLSI implementations. It is demonstrated how long transforms can be implemented with components designed to perform a short length transform. These components build into longer transforms preserving the regularity and structure of the short length transform design.

Systolic array architectures for parameterised multiplexed IIR filters

Whilst conventional bit level pipelining introduces an m cycle delay, it does allow m separate computations to be processed at throughput rates comparable to that using word level systolic arrays. We concentrate on exploiting this delay and describe a systematic method for the design of high performance multiplexed IIR filters. Two multiply and accumulate structures are identified based on shift-and-add and carry-save data organisations which can be used as building blocks in the design of IIR filters. By replacing the word level multiply and accumulate units in word level systolic structures with their equivalent bit level circuits and introducing latches to ensure correct timing, numerous architectures can be designed that process multiplexed data directly without any additional circuit overhead.

Generic scheduling methods for a linear QR array SoC processor

A scheduling method for implementing a generic linear QR array processor architecture is presented. This improves on previous work. It also considerably simplifies the derivation of schedules for a folded linear system, where detailed account has to be taken of processor cell latency. The architecture and scheduling derived provide the basis of a generator for the rapid design of System-on-a-Chip (SoC) cores for QR decomposition.

A 76-84 GHz SiGe power amplifier array employing low-loss four-way differential combining transformer

This paper presents holistic design of a novel four-way differential power-combining transformer for use in millimeter-wave power-amplifier (PA). The combiner with an inner radius of 25 µm exhibits a record low insertion loss of 1.25 dB at 83.5 GHz. It is designed to simultaneously act as a balanced-to-unbalanced converter, removing the need for additional BALUNs typically required in differential circuits. A complete circuit comprised of a power splitter, two-stage differential cascode PA array, a power combiner as well as input and output matching elements was designed and realized in SiGe technology with f/f 170/250 GHz. Measured small-signal gain of at least 16.8 dB was obtained from 76.4 to 85.3 GHz with a peak 19.5 dB at 83 GHz. The prototype delivered 12.5 dBm output referred 1 dB compression point and 14 dBm saturated output power when operated from a 3.2 V dc supply voltage at 78 GHz.