BIT-LEVEL SYSTOLIC ARRAY CIRCUIT FOR MATRIX VECTOR MULTIPLICATION.


Autoria(s): McCanny, J.V.; McWhirter, J.G.
Data(s)

01/08/1983

Resumo

A bit-level systolic array for computing matrix x vector products is described. The operation is carried out on bit parallel input data words and the basic circuit takes the form of a 1-bit slice. Several bit-slice components must be connected together to form the final result, and authors outline two different ways in which this can be done. The basic array also has considerable potential as a stand-alone device, and its use in computing the Walsh-Hadamard transform and discrete Fourier transform operations is briefly discussed.

Identificador

http://pure.qub.ac.uk/portal/en/publications/bitlevel-systolic-array-circuit-for-matrix-vector-multiplication(5bf021f2-cfae-45fc-8865-c4e88921a0f7).html

http://www.scopus.com/inward/record.url?partnerID=yv4JPVwI&eid=2-s2.0-0020799350&md5=3019411f06bda2442df4ccb80aa2161c

Idioma(s)

eng

Direitos

info:eu-repo/semantics/restrictedAccess

Fonte

McCanny , J V & McWhirter , J G 1983 , ' BIT-LEVEL SYSTOLIC ARRAY CIRCUIT FOR MATRIX VECTOR MULTIPLICATION. ' IEE proceedings. Part G. Electronic circuits and systems , vol 130 , no. 4 , pp. 125-130 .

Tipo

article