Two-port calibration of test fixtures with OSL method.

The open-short-load (OSL) method is very simple and widely used, for one-port test fixture calibration. In this paper, this method. is extended to the two-port calibration of test fixtures for the first time. The problem of phase uncertainty arising in this application has been solved. The comparison between our results and those obtained with the short-open-load-thru (SOLT) method shows that the method established is accurate enough for practical applications.

Frequency limitation in calibrating microwave test fixtures

The problem of frequency limitation arising in calibration of the test fixtures is investigated in this paper. It is found that at some frequencies periodically, the accuracy of the methods becomes very low, and. the denominators of the expressions of the required S-parameters approach zero. This conclusion can be drawn whether-the test fixtures, are symmetric or not. A good agreement between theory and experiment is obtained.

Choice of calibration equations of the TSM method

For the reciprocal-test fixtures, there are six independent S-parameters to. be determined, and the thru-short-match (TSM) calibration can provide eight calibration equations. In this paper, the relation of calibration equations is investigated. It has been shown that the four equations obtained from the measurement with a transmission standard can be used simultaneously in the calibration. Experimental results show that the different choice of equations will lead to quite different solution, and the calibration accuracy can be improved by taking advantages of the established relation among the calibration equations and properly choosing calibration equations.

Ti Schottky barrier diodes on n-type 6H-SiC

Using thermal evaporation, Ti/6H-SiC Schottky barrier diodes (SBD) were fabricated. They showed good rectification characteristics from room temperature to 200degreesC. At low current density. the current conduction mechanism follows the thermionic emission theory. These diodes demonstrated a low reverse leakage current of below 1 X 10(-4)Acm(-2). Using neon implantation to form the edge termination, the breakdown voltage was improved to be 800V. In addition. these SBDs showed superior switching characteristics.

A semiconductor laser suitably fabricated by planar technology

The semiconductor microlasers with an equilateral triangle resonator which can be fabricated by dry etching technique from the laser wafer of the edge emitting laser, are analyzed by FDTD technique and rate equations. The results show that ETR microlaser is suitable to realize single mode operation. By connecting an output waveguide to one of the vertices of the ETR, we still can get the confined modes with high quality factors. The EM microlasers are potential light sources for photonic integrated circuits.

Hybrid CMOS/VCSEL optoelectronic modules

We report some investigations on vertical cavity surface emitting laser (VCSEL) arrays and VCSEL based optoelectronic smart photonic multiple chip modules (MCM), consisting of 1x16 vertical cavity surface emitting laser array and 16-channel lasers driver 0.35 Pin CMOS circuit. The hybrid integrated multiple chip modules based on VCSEL operate at more than 2GHz in -3dB frequency bandwidth.

Small signal equivalent circuit model of vertical cavity surface emitting lasers

Small signal equivalent circuit model of vertical cavity surface emitting lasers (VCSEL's) is given in this paper. The modulation properties of VCSEL are simulated using this model in Pspice program. The simulation results are good agree with experiment data. Experiment is performed to testify the circuit model.

Observation of deep electron states in n-type Al-doped ZnS1-xTex grown by molecular beam epitaxy

Deep level transient spectroscopy (DLTS) technique was used to investigate deep electron states in n-type Al-doped ZnS1-xTex epilayers grown by molecular fiction epitaxy (MBE), Deep level transient Fourier spectroscopy (DLTFS) spectra of the Al-doped ZnS1-xTex (x = 0. 0.017, 0.04 and 0.046. respectively) epilayers reveal that At doping leads to the formation of two electron traps at 0.21 and 0.39 eV below the conduction hand. 1)DLTFS results suggest that in addition to the rules of Te as a component of [lie alloy as well as isoelectronic centers, Te is also involved in the formation of all electron trip, whose energy level relative to the conduction hand decreases a, Te composition increases.

Low power design in 100 MHz embedded SRAM

Low power design method is used in a 100MHz embedded SRAM. The embedded SRAM used in a FFT chip is divided into 16 blocks. Two-level decoders are used and only one block can be selected at one time by tristate control circuits, while other blocks are set stand-by. The SRAM cell has been optimized and the cell area has been minimized at the same time.

Scan test in 18x8 bits Booth Coding-Wallace Tree multiplier

Scan test can be inserted around hard IP cores that have not been designed with DFT approaches. An 18x18 bits Booth Coding-Wallace Tree multiplier has been designed with full custom approach with 0.61 m CMOS technology. When we reuse the multiplier in another chip, scan chain has been inserted around it to increase the fault coverage. After scan insertion, the multiplier needs 4.7% more areas and 24.4% more delay time, while the fault coverage reaches to 95%.

Residual donors in undoped LEC InP

Undoped liquid encapsulated Czochralski (LEC) InP samples have been studied by Hall effect, glow discharge mass spectroscopy (GDMS) and infrared absorption spectroscopy. A systematic discrepancy has been found between the Han electron concentration and net donor concentration measured by GDMS. The electron concentration is always higher than the net shallow donor concentration by about (3-6)x10(15)cm(-3). A hydrogen indium vacancy complex donor defect VInH4 was detected regularly by infrared absorption spectroscopy in all undoped LEC InP samples. The fact can be explained by taking into account the existence of the donor defect in as-grown undoped LEC-InP.

Artificial neural networks expecting more advanced microelectronics technology

　

JFET SOS devices: Processing and gamma radiation effects

A process for fabricating n channel JFET/SOS (junction field-effect transistors on silicon-on-sapphire) has been researched. The gate p(+)n junction was obtained by diffusion, and the conductive channel was gotten by a double ion implantation. Both enhancement and depletion mode transistors were fabricated in different processing conditions. From the results of the Co-50 gamma ray irradiation experimental we found that the devices had a good total dose radiation-hardness. When the tot;ll dose was 5Mrad(Si), their threshold voltages shift was less than 0.1V. The variation of transconductance and the channel leakage current were also little.

Improvement of CMOS SOS devices characteristics by a modified solid phase epitaxy

CMOS/SOS devices have lower carriers mobility and higher channel leakage current than bulk silicon CMOS devices. These mainly results from the defects of heteroepitaxial silicon film, especially from the defects near Si-Sapphire interface. This paper describes the experiment results of CMOS/SOS devices characteristics improved by a better epitaxial silicon quality which is obtained by a modified solid phase epitaxy.

Dependence of ultra-thin gate oxide reliability on surface cleaning approach

In this paper, we investigate the effect of silicon surface cleaning prior to oxidation on the reliability of ultra-thin oxides. It is demonstrated that chemical preoxide grown in H2SO4/H2O2 (SPM) solution prior to oxidation provides better oxide integrity than both HF-based solution dipping and preoxide grown in RCA SC1 or SC2 solutions. It is also found that the oxides with SPM preoxide exhibit better hot-carrier immunity than the RCA cleaned oxides.