Low power design in 100 MHz embedded SRAM
| Data(s) |
2001
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|---|---|
| Resumo |
Low power design method is used in a 100MHz embedded SRAM. The embedded SRAM used in a FFT chip is divided into 16 blocks. Two-level decoders are used and only one block can be selected at one time by tristate control circuits, while other blocks are set stand-by. The SRAM cell has been optimized and the cell area has been minimized at the same time. Low power design method is used in a 100MHz embedded SRAM. The embedded SRAM used in a FFT chip is divided into 16 blocks. Two-level decoders are used and only one block can be selected at one time by tristate control circuits, while other blocks are set stand-by. The SRAM cell has been optimized and the cell area has been minimized at the same time. 于2010-10-29批量导入 Made available in DSpace on 2010-10-29T06:36:41Z (GMT). No. of bitstreams: 1 2854.pdf: 292819 bytes, checksum: 34d91cbd8ea62c1b88f2cec3e3db8425 (MD5) Previous issue date: 2001 Chinese Inst Electr.; IEEE Beijing Sect.; Natl Nat Sci Fdn China.; Shanghai Municipal Sci & Technol Commiss. Chinese Acad Sci, Inst Semicond, Beijing 100083, Peoples R China Chinese Inst Electr.; IEEE Beijing Sect.; Natl Nat Sci Fdn China.; Shanghai Municipal Sci & Technol Commiss. |
| Identificador | |
| Idioma(s) |
英语 |
| Publicador |
IEEE 345 E 47TH ST, NEW YORK, NY 10017 USA |
| Fonte |
Wang DH; Qiu J; Li YG; Hou CH .Low power design in 100 MHz embedded SRAM .见：IEEE .2001 4TH INTERNATIONAL CONFERENCE ON ASIC PROCEEDINGS,345 E 47TH ST, NEW YORK, NY 10017 USA ,2001,599-602 |
| Palavras-Chave | #微电子学 |
| Tipo |
会议论文 |
