Ultralow Silicon Substrate Noise Crosstalk Using Metal Faraday Cages in an SOI Technology

In mixed signal integrated circuits noise from the digital circuitry can upset the sensitive analogue circuitry. The Faraday cage structure reported here is based on the unique ground plane SOI technology developed some of the authors. The suppression of crosstalk achieved is an order of magnitude greater than that previously published for frequencies up to 10 GHz. The significance of the technology will be even greater as the operating frequency is increased. This collaborative EPSRC project was judge as tending to outstanding.

SiGe HBTs on Bonded SOI Incorporating Buried Silicide Layers

The performance of silicon bipolar transistors has been significantly improved by the use of ultra narrow base layers of SiGe. To further improve device performance by minimising parasitic resistance and capacitance the authors produced an unique silicon-on-insulator (SOI) substrate incorporating a buried tungsten disilicide layer. This structure forms the basis of a recent submission by Zarlink Semiconductors ( Silvaco, DeMontfort & Queen�s) to DTI for high voltage devices for automotive applications. The Queen�s part of the original EPSRC project was rated as tending to outstanding.

Effect of Rapid Thermal Annealing on the Structure and Magnetic Properties of Chemical Vapour Deposition Cobalt Layers

Future read heads in hard disc storage require high conformal coatings of metal magnetic layers over high aspect ratio profiles. This paper describes pioneering work on the use of MOCVD for the deposition of cobalt layers. While pure cobalt layers could be deposited at 400C their magnetic properties are poor. It was found that the magnetic properties of the layers could be significantly enhanced with an optimised rapid thermal anneal. This work was sponsored by Seagate Technology and led to a follow up PhD studentship on the co-deposition of cobalt and iron by MOCVD.

Thin film sputtered silicon for silicon wafer bonding applications

The transfer of functional integrated circuit layers to other substrates is being investigated for smart-sensors, MEMS, 3-D ICs and mixed semiconductor circuits. There is a need for a planarisation and bondable layer which can be deposited at low temperature and which is IC compatible. This paper describes for the first time the successful use of sputtered silicon in this role for applications as outlined above where high temperature post bond anneals are not required. It also highlights the problems of using sputtered silicon as a bonding layer in applications where post bond temperatures greater than 400C are required.