A High-Performance Silicon Electro-Optic Phase Modulator with a Triple MOS Capacitor

We propose and analyze a novel Si-based electro-optic modulator with an improved metal-oxide-semiconductor (MOS) capacitor configuration integrated into silicon-on-insulator (SOI).Three gate-oxide layers embedded in the silicon waveguide constitute a triple MOS capacitor structure,which boosts the modulation efficiency compared with a single MOS capacitor.The simulation results demonstrate that the VπLπ product is 2.4V·cm.The rise time and fall time of the proposed device are calculated to be 80 and 40ps from the transient response curve,respectively,indicating a bandwidth of 8GHz.The phase shift efficiency and bandwidth can be enhanced by rib width scaling.

Fabrication of a SOI Based Channel-shifted Multimode Interference Coupler

A silicon-on-insulator based channel-shifted multimode interference coupler is designed and fabricated. A two dimensional beam propagation method is used to analyze the dependence of coupler′s performances on the width and length of the multimode waveguide. The device fabricated has a power shift ratio of 73 and an excess loss of about 2.2 dB. An enhancement of fabrication accuracies could further improve the coupler performances.

SOI thermo-optic modulator with fast response

Silicon-on-insulator (SOI) technology offers tremendous potential for integration of optoelectronic functionson a silicon wafer. In this letter, a 1 * 1 multimode interference (MMI) Mach-Zender interferometer(MZI) thermo-optic modulator fabricated by wet-etching method is demonstrated. The modulator has anextinction ratio of -11.0 dB, extra loss of -4.9 dB and power consumption of 420 mW. The response timeis less than 30μs.

Temperature Dependence of Characteristics for Multimode Interference Based 3-dB Coupler in SOI

The temperature dependence of characteristics for multimode interference (MMI) based 3-dB coupler in silicon-on-insulator is analyzed, which originates from the relatively high thermo-optic coefficient of silicon. For restricted interference 3-dB MMI coupler, the output power uniformity is ideally 0 at room temperature and becomes 0. 32 dB when temperature rises up to 550 K. For symmetric interference 3-dB MMI coupler, the power uniformity keeps ideally 0 due to its intrinsic symmetric interference mechanism. With the temperature rising, the excess loss of the both devices increases. The performance deterioration due to temperature variety is more obvious to restricted interference MMI 3-dB coupler, comparing with that of symmetric interference MMI 3-dB coupler.

一种新型SOI Mach-Zehnder干涉型电光调制器的设计

在超紧缩双曲锥形3 dB多模干涉耦合器的基础上，设计了一种新的Silicon-on-insulator (SOI) Mach-Zehnder干涉型电光调制器。与传统的Y分支器相比，双曲锥形3 dB耦合器的制作容差大，而长度缩短了近30％，使得整个器件的尺寸大幅减小。调制区采用横向注入的PIN结构，模拟结果表明

SOI集成光电子器件

Silicon-on-insulator (SOI)集成光电子器件的工艺与标准CMOS工艺完全兼容，采用SOI技术可以实现低成本的整片集成光电子回路。文章回顾了近几年来SOI集成光电子器件的发展以及一些最新的研究进展。

Hybrid integration and packaging of grating-coupled silicon photonics

This thesis covers both the packaging of silicon photonic devices with fiber inputs and outputs as well as the integration of laser light sources with these same devices. The principal challenge in both of these pursuits is coupling light into the submicrometer waveguides that are the hallmark of silicon-on-insulator (SOI) systems. Previous work on grating couplers is leveraged to design new approaches to bridge the gap between the highly-integrated domain of silicon, the Interconnected world of fiber and the active region of III-V materials. First, a novel process for the planar packaging of grating couplers with fibers is explored in detail. This technology allows the creation of easy-to-use test platforms for laser integration and also stands on its own merits as an enabling technology for next-generation silicon photonics systems. The alignment tolerances of this process are shown to be well-suited to a passive alignment process and for wafer-scale assembly. Furthermore, this technology has already been used to package demonstrators for research partners and is included in the offerings of the ePIXfab silicon photonics foundry and as a design kit for PhoeniX Software’s MaskEngineer product. After this, a process for hybridly integrating a discrete edge-emitting laser with a silicon photonic circuit using near-vertical coupling is developed and characterized. The details of the various steps of the design process are given, including mechanical, thermal, optical and electrical steps. The interrelation of these design domains is also discussed. The construction process for a demonstrator is outlined, and measurements are presented of a series of single-wavelength Fabry-Pérot lasers along with a two-section laser tunable in the telecommunications C-band. The suitability and potential of this technology for mass manufacture is demonstrated, with further opportunities for improvement detailed and discussed in the conclusion.

Electrical Characterisation of SOI Substrates Incorporating WSix Ground Planes

Silicon-on-insulator (SOI) substrates incorporating tungsten silicide ground planes (GPs) have been shown to offer the lowest reported crosstalk figure of merit for application in mixed signal integrated circuits. The inclusion of the silicide layer in the structure may lead to stress or defects in the overlying SOI layers and resultant degradation of device performance. It is therefore essential to establish the quality of the silicon on the GPSOI substrate. MOS capacitor structures have been employed in this paper to characterize these GPSOI substrates for the first time. High quality MOS capacitor characteristics have been achieved with minority carrier lifetime of similar to 0.8 ms. These results show that the substrate is suitable for device manufacture with no degradation in the silicon due to stress or metallic contamination resulting from the inclusion of the underlying silicide layer.

Investigation of precision grinding process for production of silicon diaphragms

The application of precision grinding for the formation of a silicon diaphragm is investigated. The test structures involved 2-6 mm diam diaphragms with thicknesses in the range of 25-150 //m. When grinding is performed without supporting the diaphragm, bending occurs due to nonuniform removal of the silicon material over the diaphragm region. The magnitude of bending depends on the µNal thickness of the diaphragm. The results demonstrate that the use of a porous silicon support can significantly reduce the amount of bending, by a factor of up to 300 in the case of 50 m thick diaphragms. The use of silicon on insulator (SOI) technology can also suppress or eliminate bending although this may be a less economical process. Stress measurements in the diaphragms were performed using x-ray and Raman spectroscopies. The results show stress of the order of 1 X107-! X108 Pa in unsupported and supported by porous silicon diaphragms while SOI technology provides stress-free diaphragms. Results obtained from finite element method analysis to determine deterioration in the performance of a 6 mm diaphragm due to bending are presented. These results show a 10% reduction in performance for a 75 µm thick diaphragm with bending amplitude of 30 fim, but negligible reduction if the bending is reduced to

Analog performance of double gate SOI transistors

Double gate fully depleted silicon-on-insulator (DGSOI) is recognized as a possible solution when the physical gate length L-G reduces to 25nm for the 65nm node on the ITRS CMOS roadmap. In this paper, scaling guidelines are introduced to optimally design a nanoscale DGSOI. For this reason, the sensitivity of gain, f(T) and f(max) to each of the key geometric and technological parameters of the DGSOI are assessed and quantified using MixedMode simulation. The impact of the parasitic resistance and capacitance on analog device performance is systematically analysed. By comparing analog performance with a single gate (SG), it has been found that intrinsic gain in DGSOI is 4 times higher but its fT was found to be comparable to that of SGSOI at different regions of transistor operation. However, the extracted fmax in SG SOI was higher (similar to 40%) compared to DGSOI due to its lower capacitance.

Fabrication and characterisation of high resistivity SOI substrates for monolithic high energy physics detectors

Silicon on Insulator (SOI) substrates offer a promising platform for monolithic high energy physics detectors with integrated read-out electronics and pixel diodes. This paper describes the fabrication and characterisation of specially-configured SOI substrates using improved bonded wafer ion split and grind/polish technologies. The crucial interface between the high resistivity handle silicon and the SOI buried oxide has been characterised using both pixel diodes and circular geometry MOS transistors. Pixel diode breakdown voltages were typically greater than 100V and average leakage current densities at 70 V were only 55 nA/ sq cm. MOS transistors subjected to 24 GeV proton irradiation showed an increased SOI buried oxide trapped charge of only 3.45x1011cn-2 for a dose of 2.7Mrad

Improved Thermal Performance of SOI Using Compound Buried Layer

The buried oxide (BOX) layer in silicon on insulator (SOI) was replaced by a compound buried layer (CBL) containing layers of SiO2, polycrystalline silicon (polysilicon), and SiO2. The undoped polysilicon in the CBL acted as a dielectric with a higher thermal conductivity than SiO2. CBL provides a reduced thermal resistance with the same equivalent oxide thickness as a standard SiO2 buried layer. Thermal resistance was further reduced by lateral heat flow through the polysilicon. Reduction in thermal resistance by up to 68% was observed, dependent on polysilicon thickness. CBL SOI substrates were designed and manufactured to achieve a 40% reduction in thermal resistance compared with an 1.0-μm SiO2 BOX. Power bipolar transistors with an active silicon layer thickness of 13.5 μm manufactured on CBL SOI substrates showed a 5%-17% reduction in thermal resistance compared with the standard SOI. This reduction was dependent on transistor layout geometry. Between 65% and 90% of the heat flow from these power transistors is laterally through the thick active silicon layer. Analysis confirmed that CBL SOI provided a 40% reduction in the vertical path thermal resistance. Devices employing thinner active silicon layers will achieve the greater benefit from reduction in vertical path thermal resistance offered by CBL SOI.