SLA Brokering and Bandwidth Reservation Negotiation Schemes for QoS-aware Internet

We present a novel Service Level Agreement (SLA)-driven service provisioning architecture, which enables dynamic and flexible bandwidth reservation schemes on a per-user or per-application basis. Various session level SLA negotiation schemes involving bandwidth allocation, service start time and service duration parameters are introduced and analyzed. The results show that these negotiation schemes can be utilized for the benefit of both end users and network providers in achieving the highest individual SLA optimization in terms of key Quality of Service (QoS) metrics and price. The inherent characteristics of software agents such as autonomy, adaptability and social abilities offer many advantages in this dynamic, complex, and distributed network environment especially when performing Service Level Agreements (SLA) definition negotiations and brokering tasks. This article also presents a service broker prototype based on Fujitsu's Phoenix Open Agent Mediator (OAM) agent technology, which was used to demonstrate a range of SLA brokering scenarios.

'Grooming' and the Sexual Abuse of Children:Institutional, Internet and Familial Dimensions

‘Grooming’ and the Sexual Abuse of Children: Institutional, Internet and Familial Dimensions critically examines the official and popular discourses on grooming, predominantly framed within the context of on-line sexual exploitation and abuse committed by strangers, and institutional child abuse committed by those in positions of trust.

Set against the broader theoretical framework of risk, security and governance, this book argues that due to the difficulties of drawing clear boundaries between innocuous and harmful motivations towards children, pre-emptive risk-based criminal law and policy are inherently limited in preventing, targeting and criminalising ‘grooming’ behaviour prior to the manifestation of actual harm. Through examination of grooming against the complexities of the onset of sexual offending against children and its actual role in this process, the author broadens existing discourses by providing a fuller, more nuanced conceptualisation of grooming, including its role in intra-familial and extra-familial contexts. There is also timely discussion of new and emerging forms of grooming, such as ‘street’ or ‘localised’ grooming, as typified by recent cases in Rochdale and Oldham, and ‘peer-to-peer’ grooming.

The first inter-disciplinary, thematic, and empirical investigation of grooming in a multi-jurisdictional context, ‘Grooming’ and the Sexual Abuse of Children draws on extensive empirical research in the form of over fifty interviews with professionals, working in the fields of sex offender risk assessment, management or treatment, as well as child protection or victim support in the four jurisdictions of the United Kingdom and the Republic of Ireland. Impeccably presented and meticulously considered, this book will be of interest to criminologists and those working and studying in the field of policing and criminal justice studies, as well as policy makers and practitioners in the areas of child protection and sex offender management.

SVM Training Phase Reduction Using Dataset Feature Filtering for Malware Detection

N-gram analysis is an approach that investigates the structure of a program using bytes, characters, or text strings. A key issue with N-gram analysis is feature selection amidst the explosion of features that occurs when N is increased. The experiments within this paper represent programs as operational code (opcode) density histograms gained through dynamic analysis. A support vector machine is used to create a reference model, which is used to evaluate two methods of feature reduction, which are 'area of intersect' and 'subspace analysis using eigenvectors.' The findings show that the relationships between features are complex and simple statistics filtering approaches do not provide a viable approach. However, eigenvector subspace analysis produces a suitable filter.

Systolic building block for high performance recursive filtering

A novel bit level systolic array is presented that can be used as a building block in the construction of recursive digital filters. The circuit accepts bit-parallel input data, is pipelined at the bit level, and exhibits a very high throughput rate. The most important feature of the circuit is that it allows recursive operations to be implemented directly without incurring the large m cycle latency (where m is approximately the word length) normally associated with such systems. The use of this circuit in the construction of both first- and second-order IIR (infinite-impulse-response) filters is described.

Algorithms and architectures for high performance recursive filtering

Recently, a number of most significant digit (msd) first bit parallel multipliers for recursive filtering have been reported. However, the design approach which has been used has, in general, been heuristic and consequently, optimality has not always been assured. In this paper, msd first multiply accumulate algorithms are described and important relationships governing the dependencies between latency, number representations, etc are derived. A more systematic approach to designing recursive filters is illustrated by applying the algorithms and associated relationships to the design of cascadable modules for high sample rate IIR filtering and wave digital filtering.

High performance VLSI architecture for Wave Digital Filtering

The application of fine grain pipelining techniques in the design of high performance Wave Digital Filters (WDFs) is described. It is shown that significant increases in the sampling rate of bit parallel circuits can be achieved using most significant bit (msb) first arithmetic. A novel VLSI architecture for implementing two-port adaptor circuits is described which embodies these ideas. The circuit in question is highly regular, uses msb first arithmetic and is implemented using simple carry-save adders. © 1992 Kluwer Academic Publishers.

Bit-Level systolic architectures for high performance IIR filtering

Several novel systolic architectures for implementing densely pipelined bit parallel IIR filter sections are presented. The fundamental problem of latency in the feedback loop is overcome by employing redundant arithmetic in combination with bit-level feedback, allowing a basic first-order section to achieve a wordlength-independent latency of only two clock cycles. This is extended to produce a building block from which higher order sections can be constructed. The architecture is then refined by combining the use of both conventional and redundant arithmetic, resulting in two new structures offering substantial hardware savings over the original design. In contrast to alternative techniques, bit-level pipelinability is achieved with no net cost in hardware. © 1989 Kluwer Academic Publishers.

Pipelined two-port adaptor for wave digital filtering

The application of fine-grain pipelining techniques in the design of high-performance wave digital filters (WDFs) is described. The problems of latency in feedback loops can be significantly reduced if computations are organized most significant, as opposed to least significant, bit first and if the results are fed back as soon as they are formed. The result is that chips can be designed which offer significantly higher sampling rates than otherwise can be obtained using conventional methods. How these concepts can be extended to the more challenging problem of WDFs is discussed. It is shown that significant increases in the sampling rate of bit-parallel circuits can be achieved using most significant bit first arithmetic.

Bit-level systolic arrays for IIR filtering.

A novel bit-level systolic array architecture for implementing IIR (infinite-impulse response) filter sections is presented. A first-order section achieves a latency of only two clock cycles by using a radix-2 redundant number representation, performing the recursive computation most significant digit first, and feeding back each digit of the result as soon as it is available. The design is extended to produce a building block from which second- and higher-order sections can be connected.

Optimized bit level architectures for IIR filtering

Optimized circuits for implementing high-performance bit-parallel IIR filters are presented. Circuits constructed mainly from simple carry save adders and based on most-significant-bit (MSB) first arithmetic are described. Two methods resulting in systems which are 100% efficient in that they are capable of sampling data every cycle are presented. In the first approach the basic circuit is modified so that the level of pipelining used is compatible with the small, but fixed, latency associated with the computation in question. This is achieved through insertion of pipeline delays (half latches) on every second row of cells. This produces an area-efficient solution in which the throughput rate is determined by a critical path of 76 gate delays. A second approach combines the MSB first arithmetic methods with the scattered look-ahead methods. Important design issues are addressed, including wordlength truncation, overflow detection, and saturation.