Architecture and Construction Management at Queens University Belfast:Regional Cultural Centre

The Regional Cultural Centre in Letterkenny is a new 2000sqm arts center containing theatre, galleries, workshops and ancillary offices. The site is set back from the street, on high ground with good views. The form and envelope of the building was derived from geometrically connecting the site with the town’s two other main public buildings, the Cathedral (1901) and new Civic Offices (2002, also designed by MacGabhann Architects). This geometrical connection or vectors informed the geometry and shape of the building. This urban matrix of geometrically connecting three corner stones of society, namely the ecclesiastical headquarters, the administrative head quarters and the art centre helps to improve the town planning and urban design of the disparate and chaotic development that Letterkenny has become.
The large cantilever, which houses a 300sqm gallery, is aligned towards the Civic Offices, marks the entrance, and signifies a change of direction of the pedestrian route past the building, like a modern day obelisk.
The circulation routes and stairs internally provide views towards the civic offices and cathedral, thus reinforcing the connection between the three buildings and helps visitors make some sense of Letterkenny as an urban center. The main stairs and vertical circulation are contained behind the large glazed foyer, which is framed to be viewed externally like a proscenium stage, with visitors to the building passively acting their routes through the building.

A design model: the Autism Spectrum Disorder Classroom Design Kit

Architects and designers have a responsibility to provide an inclusive built environment. However for those with a diagnosis of Autism Spectrum Disorder (ASD), the built environment can be a frightening and confusing place, difficult to negotiate and tolerate. The challenge of integrating more fully into society is denied by an alienating built environment. For ASD pupils in a poorly designed school, their environment can distance them from learning. Instead, if more at ease in their surroundings, in an ASD-friendly environment, the ASD pupil stands a greater chance of doing better.

However a difficulty exists in that most architects are not knowledgeable in designing for those with ASD. Any available design guidelines for architects tend, because of the inherent difficulties associated with a spectrum, to be general in their information. Therefore, if wanting to provide an ASD-friendly learning environment, there is a need to ensure that teachers, as the experts, can most clearly and effectively impart their knowledge and requirements to architects.

This paper sets out the challenges and difficulties inherent in the design process when designing for ASD. It then sets out an alternative strategy to the usual method of drawing-centric dialogue between teacher and architect by using models instead as a basis for a more common language. An ASD Classroom Design Kit was designed and developed by Queen’s University of Belfast Architecture students. It was then used by ASD teaching staff from the Southern Education and Library Board in Northern Ireland as a case study to trial its effectiveness. The paper outlines how the study was carried out before concluding with reflections by both teaching staff and architect on using the ASD Classroom Design Kit.

It is hoped that this paper will firstly highlight the need for better dialogue between expert and architect when considering ASD and the Built Environment and secondly, that it may encourage others to consider using models to convey their ideas and knowledge when designing, not just for ASD, but for other Special Educational Needs and disabilities.

High performance VLSI architecture for division and square root

A novel high performance bit parallel architecture to perform square root and division is proposed. Relevant VLSI design issues have been addressed. By employing redundant arithmetic and a semisystolic schedule, the throughput has been made independent of the size of the array.

Design and test of a bit parallel 2nd order IIR filter structure

Test procedures for a pipelined bit-parallel IIR filter chip which maximally exploit its regularity are described. It is shown that small modifications to the basic architecture result in significant reductions in the number of test patterns required to test such chips. The methods used allow 100% fault coverage to be achieved using less than 1000 test vectors for a chip which has 12 bit data and coefficients.

High performance VLSI architecture for Wave Digital Filtering

The application of fine grain pipelining techniques in the design of high performance Wave Digital Filters (WDFs) is described. It is shown that significant increases in the sampling rate of bit parallel circuits can be achieved using most significant bit (msb) first arithmetic. A novel VLSI architecture for implementing two-port adaptor circuits is described which embodies these ideas. The circuit in question is highly regular, uses msb first arithmetic and is implemented using simple carry-save adders. © 1992 Kluwer Academic Publishers.

Rapid design of discrete orthonormal wavelet transforms

A methodology which allows a non-specialist to rapidly design silicon wavelet transform cores has been developed. This methodology is based on a generic architecture utilizing time-interleaved coefficients for the wavelet transform filters. The architecture is scaleable and it has been parameterized in terms of wavelet family, wavelet type, data word length and coefficient word length. The control circuit is designed in such a way that the cores can also be cascaded without any interface glue logic for any desired level of decomposition. This parameterization allows the use of any orthonormal wavelet family thereby extending the design space for improved transformation from algorithm to silicon. Case studies for stand alone and cascaded silicon cores for single and multi-stage analysis respectively are reported. The typical design time to produce silicon layout of a wavelet based system has been reduced by an order of magnitude. The cores are comparable in area and performance to hand-crafted designs. The designs have been captured in VHDL so they are portable across a range of foundries and are also applicable to FPGA and PLD implementations.

Design and implementation of the symmetrically extended 2-D wavelet transform

The inclusion of the Discrete Wavelet Transform in the JPEG-2000 standard has added impetus to the research of hardware architectures for the two-dimensional wavelet transform. In this paper, a VLSI architecture for performing the symmetrically extended two-dimensional transform is presented. This architecture conforms to the JPEG-2000 standard and is capable of near-optimal performance when dealing with the image boundaries. The architecture also achieves efficient processor utilization. Implementation results based on a Xilinx Virtex-2 FPGA device are included.

Reconfigurable full-search video motion estimation architecture

In this paper, a new reconfigurable multi-standard architecture is introduced for integer-pixel motion estimation and a standard-cell based chip design study is presented. This has been designed to cover most of the common block-based video compression standards, including MPEG-2, MPEG-4, H.263, H.264, AVS and WMV-9. The architecture exhibits simpler control, high throughput and relative low hardware cost and highly competitive when compared with excising designs for specific video standards. It can also, through the use of control signals, be dynamically reconfigured at run-time to accommodate different system constraint such as the trade-off in power dissipation and video-quality. The computational rates achieved make the circuit suitable for high end video processing applications. Silicon design studies indicate that circuits based on this approach incur only a relatively small penalty in terms of power dissipation and silicon area when compared with implementations for specific standards.

Rapid design of a single chip adaptive beamformer

This paper presents the design of a single chip adaptive beamformer which contains 5 million transistors and can perform 50 GigaFlops. The core processor of the adaptive beamformer is a QR-array processor implemented on a fully efficient linear systolic architecture. The paper highlights a number of rapid design techniques that have been used to realize the design. These include an architecture synthesis tool for quickly developing the circuit architecture and the utilization of a library of parameterizable silicon intellectual property (IP) cores, to rapidly develop the circuit layouts.

Rapid VLSI design of biorthogonal wavelet transform cores

A rapid design methodology for biorthogonal wavelet transform cores has been developed. This methodology is based on a generic, scaleable architecture for the wavelet filters. The architecture offers efficient hardware utilization by combining the linear phase property of biorthogonal filters with decimation in a MAC based implementation. The design has been captured in VHDL and parameterized in terms of wavelet type, data word length and coefficient word length. The control circuit is embedded within the cores and allows them to be cascaded without any interface glue logic for any desired level of decomposition. The design time to produce silicon layout of a biorthogonal wavelet based system is typically less than a day. The resulting silicon cores produced are comparable in area and performance to hand-crafted designs. The designs are portable across a range of foundries and are also applicable to FPGA and PLD implementations.

Design of interlock-free combined allocators for Networks-on-Chip

This paper presents a thorough investigation of the combined allocator design for Networks-on-Chip (NoC). Particularly, we discuss the interlock of the combined NoC allocator, which is caused by the lock mechanism of priority updating between the local and global arbiters. Architectures and implementations of three interlock-free combined allocators are presented in detail. Their cost, critical path, as well as network level performance are demonstrated based on 65-nm standard cell technology.

Critical Dialogue in Architecture Studio: Peer Interaction and Feedback

Most tutors in architecture education regard studio-based learning to be rich in feedback due to is dialogic nature. Yet, student perceptions communicated via audits such as the UK National Student Survey appear to contradict this assumption and challenge the efficacy of design studio as a truly discursive learning setting. This paper presents findings from a collaborative study that was undertaken by the Robert Gordon University, Aberdeen, and Queen’s University Belfast that develop a deeper understanding of the role that peer interaction and dialogue plays within feedback processes, and the value that students attribute to these within the overall learning experience.

The paper adopts a broad definition of feedback, with emphasis on formative processes, and including the various kinds of dialogue that typify studio-based learning, and which constitute forms of guidance, direction, and reflection. The study adopted an ethnographic approach, gathering data on student and staff perceptions over the course of an academic year, and utilising methods embracing both quantitative and qualitative data.

The study found that the informal, socially-based peer interaction that characterises the studio is complementary to, and quite distinct from, the learning derived through tutor interaction. The findings also articulate the respective properties of informal and formally derived feedback and the contribution each makes to the quality of studio-based learning. It also identifies limitations in the use or value of peer learning, understanding of which is valuable to enhancing studio learning in architecture.

Understanding Student and Staff Perceptions of Feedback in Architecture: Summary Report

This report presents the results of a collaborative project between Queens University, Belfast and the Robert Gordon University, Aberdeen, and builds on a dialogue initiated during Session 2009-10 through which course guidance and feedback received by students was identified as an area requiring deeper understanding in order to enhance current practice

Efficient Architectural Design Space Exploration via Predictive Modeling

Efficiently exploring exponential-size architectural design spaces with many interacting parameters remains an open problem: the sheer number of experiments required renders detailed simulation intractable.We attack this via an automated approach that builds accurate predictive models. We simulate sampled points, using results to teach our models the function describing relationships among design parameters. The models can be queried and are very fast, enabling efficient design tradeoff discovery. We validate our approach via two uniprocessor sensitivity studies, predicting IPC with only 1–2% error. In an experimental study using the approach, training on 1% of a 250-K-point CMP design space allows our models to predict performance with only 4–5% error. Our predictive modeling combines well with techniques that reduce the time taken by each simulation experiment, achieving net time savings of three-four orders of magnitude.