Design of interlock-free combined allocators for Networks-on-Chip
Data(s) |
2012
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Resumo |
This paper presents a thorough investigation of the combined allocator design for Networks-on-Chip (NoC). Particularly, we discuss the interlock of the combined NoC allocator, which is caused by the lock mechanism of priority updating between the local and global arbiters. Architectures and implementations of three interlock-free combined allocators are presented in detail. Their cost, critical path, as well as network level performance are demonstrated based on 65-nm standard cell technology. |
Identificador | |
Idioma(s) |
eng |
Publicador |
Institute of Electrical and Electronics Engineers (IEEE) |
Direitos |
info:eu-repo/semantics/restrictedAccess |
Fonte |
Lu , Y , Chen , C , McCanny , J V & Sezer , S 2012 , Design of interlock-free combined allocators for Networks-on-Chip . in IEEE International SOC Conference (SOCC), 2012 . Institute of Electrical and Electronics Engineers (IEEE) , pp. 358 - 363 . DOI: 10.1109/SOCC.2012.6398332 |
Palavras-Chave | #/dk/atira/pure/subjectarea/asjc/1700/1708 #Hardware and Architecture #/dk/atira/pure/subjectarea/asjc/2200/2207 #Control and Systems Engineering #/dk/atira/pure/subjectarea/asjc/2200/2208 #Electrical and Electronic Engineering |
Tipo |
contributionToPeriodical |