A novel noise optimization technique for inductively degenerated CMOS LNA

This paper proposes a novel noise optimization technique. The technique gives analytical formulae for the noise performance of inductively degenerated CMOS low noise amplifier (LNA) circuits with an ideal gate inductor for a fixed bias voltage and nonideal gate inductor for a fixed power dissipation, respectively, by mathematical analysis and reasonable approximation methods. LNA circuits with required noise figure can be designed effectively and rapidly just by using hand calculations of the proposed formulae. We design a 1.8 GHz LNA in a TSMC 0.25 pan CMOS process. The measured results show a noise figure of 1.6 dB with a forward gain of 14.4 dB at a power consumption of 5 mW, demonstrating that the designed LNA circuits can achieve low noise figure levels at low power dissipation.

1-Gb/s zero-pole cancellation CMOS transimpedance amplifier for Gigabit Ethernet applications

A zero-pole cancellation transimpedance amplifier (TIA) has been realized in 0.35 μm RF CMOS tech nology for Gigabit Ethernet applications. The TIA exploits a zero-pole cancellation configuration to isolate the input parasitic capacitance including photodiode capacitance from bandwidth deterioration. Simulation results show that the proposed TIA has a bandwidth of 1.9 GHz and a transimpedance gain of 65 dB·Ω for 1.5 pF photodiode capaci tance, with a gain-bandwidth product of 3.4 THz·Ω. Even with 2 pF photodiode capacitance, the bandwidth exhibits a decline of only 300 MHz, confirming the mechanism of the zero-pole cancellation configuration. The input resis tance is 50 Ω, and the average input noise current spectral density is 9.7 pA/(Hz)~(1/2). Testing results shows that the eye diagram at 1 Gb/s is wide open. The chip dissipates 17 mW under a single 3.3 V supply.

低温漂高电源抑制的CMOS片上电流源

设计了一种用于驱动电路和模数转换器的片上电流源,该结构利用带隙基准的方法产生了一个与温度无关的参考电平,同时为了满足高电源抑制的要求,电流源中采用了运算放大器的负反馈环路来抑制电源到输出的增益,从而使输出电平与电源电压无关,然后通过电阻把电压转化为电流.该电路在0.35,μm、3.3 V的工艺下实现,芯片面积为0.03 mm~2.仿真和测试结果表明,该电流源的温度系数为8.7×10~(-6)/℃,在2.6～4 V的电源电压下均能正常工作,达到了系统要求.

与CMOS兼容的硅基波导型光电探测器的研究

硅基波导型光电探测器作为一类重要的光电探测器,由于其能与标准的CMOS工艺兼容以及制备工艺简单等性能,因而在光电子单片集成方面具备广阔的市场应用前景.文章着重阐述了通过离子注入引入深能级、Ge/Si自组装岛、SOI波导共振腔增强和AlGaInAs-Si混合集成等四种方式来制备硅基光电探测器的研究现状和研究进展,并对四类器件的结构,制作工艺和光电性能指标进行了详细地介绍.

A Low Power Dissipation Wide-Band CMOS Frequency Synthesizer for a Dual-Band GPS Receiver

This paper presents a wide tuning range CMOS frequency synthesizer for a dual-band GPS receiver,which has been fabricated in a standard 0.18μm RF CMOS process. With a high Q on-chip inductor, the wide-band VCO shows a tuning range from 2 to 3.6GHz to cover 2.45 and 3.14GHz in case of process corner or temperature variation,with a current consumption varying accordingly from 0.8 to 0.4mA,from a 1.8V supply voltage. Measurement results show that the whole frequency synthesizer consumes very low power of 5.6mW working at L1 band with in-band phase noise less than - 82dBc/Hz and out-of-band phase noise about - ll2dBc/Hz at 1MHz offset from a 3. 142GHz carrier. The performance of the frequency synthesizer meets the requirements of GPS applications very well.

一种性能优良稳定的微功耗CMOS电压积分器

本文提出了一种电源波动影响弱、低温飘、微功耗（〈1μw）的CMOS电压型积分器电路。它利用自偏置的恒流源电路结构以及MOSFETs的亚阈值特性产生一个nA级的恒流源，通过控制电路实现对电容充放电来获得积分电压。并且对电路结构、器件类型和器件尺寸进行了优化。仿真结果表明，得到了独立于电源电压、低温度系数、微功耗的积分电压。

CMOS超高频整流器

提出了一个适用于无源UHF RFID标签芯片的全CMOS整流器.整流器包括射频-直流转换电路、偏置电路、直流-直流转换电路和振荡器电路.整流器的工作频率范围是860～960 MHz.基于0.18μm,1p6m的标准数字CMOS工艺,设计并实现了无源UHF RFID标签芯片的整流器.该设计采用开关电容电路技术动态地消除了CMOS管开启电压的问题,在标准数字CMOS工艺下实现了高效率的超高频整流器.整流器的面积为180μm×140μm.当输入900MHz,-16dBm的射频信号时,整流器的输出电压为1.2V,启动时间为980μs.

A High Speed, 12-Channel Parallel, Monolithic Integrated CMOS OEIC Receiver

The design and fabrication of a high speed, 12-channel monolithic integrated CMOS optoelectronic integrated circuit(OEIC) receiver are reported.Each channel of the receiver consists of a photodetector,a transimpedance amplifier,and a post-amplifier.The double photodiode structure speeds up the receiver but hinders responsivity.The adoption of active inductors in the TIA circuit extends the-3dB bandwidth to a higher level.The receiver has been realized in a CSMC 0.6μm standard CMOS process.The measured results show that a single channel of the receiver is able to work at bit rates of 0.8～1.4Gb/s. Altogether, the 12-channel OEIC receiver chip can be operated at 15Gb/s.

MS/RF CMOS工艺兼容的光电探测器模拟与测试

设计了一种新型的与MS/RF CMOS工艺全兼容、带深n阱(DNW)、浅沟槽隔离(STI)的双光电探测器,分析了其工作机理,用器件模拟软件ATLAS对其暗电流、响应电流、光调制频率响应和波长响应进行了模拟.采用TSMC 0.18 μm MS/RF CMOS工艺进行了流片,对芯片进行了暗电流和响应度的测试.模拟和测试结果均表明,该探测器与常规双光电探测器相比,具有较低的暗电流和较高的响应度.

Total Dose Radiation-Hard 0. SOI CMOS Transistors and ASIC

This paper presents the total dose radiation performance of 0. S^m SOI CMOS devices fabricated with full dose SIMOX technology. The radiation performance is characterized by threshold voltage shifts and leakage currents of transistors and standby currents of ASIC as functions of the total dose up to 500krad(Si) .The experimental results show that the worst case threshold voltage shifts of front channels are less than 320mV for pMOS transistors under off-gate radiation bias at lMrad(Si) and less than 120mV for nMOS transistors under on-gate radiation bias. No significant radiation-induced leakage current is observed in transistors to lMrad(Si). The standby currents of ASIC are less than the specification of 5μA over the total dose range of 500krad(Si).

基于RTD与CMOS的新型数字电路设计

纳米电子器件RTD与CMOS电路结合，这种新型电路不仅保持了CMOS动态电路的所有优点，而且在工作速度、功耗、集成度以及电路噪声免疫性方面都得到了不同程度的改善和提高。文中对数字电路中比较典型的可编程逻辑门、全加器电路进行了设计与模拟，并在此基础上对4*4阵列纳米流水线乘法器进行了结构设计。同时讨论了在目前硅基RTD器件较低的PVCR值情况下实现相应电路的可行性。