An improved gate driver for power MOSFETs using a cascode configuration

To overcome the limitations of existing gate drive topologies an improved gate drive concept is proposed to provide fast, controlled switching of power MOSFETs. The proposed topology exploits the cascode configuration with the inclusion of an active gate clamp to ensure that the driven MOSFET may be turned off under all load conditions. Key operating principles and advantages of the proposed gate drive topology are discussed. Characteristic waveforms are investigated via simulation and experimentation for the cascode driver in an inductive switching application at 375V and 10A. Experimental waveforms compared well with simulations with long gate charging delays (including the Miller plateau) being eliminated from the gate voltage waveform.

Comparison of the gate drive parameter space for driving power MOSFETs using conventional and cascode configurations

Conventional voltage driven gate drive circuits utilise a resistor to control the switching speed of power MOS-FETs. The gate resistance is adjusted to provide controlled rate of change of load current and voltage. The cascode gate drive configuration has been proposed as an alternative to the conventional resistor-fed gate drive circuit. While cascode drive is broadly understood in the literature the switching characteristics of this topology are not well documented. This paper explores, through both simulation and experimentation, the gate drive parameter space of the cascode gate drive configuration and provides a comparison to the switching characteristics of conventional gate drive.

Characterisation of the cascode gate drive of power MOSFETs in clamped inductive switching applications

This thesis proposes a novel gate drive circuit to improve the switching performance of MOSFET power switches in power electronic converters. The proposed topology exploits the cascode configuration, allowing the minimisation of switching losses in the presence of practical circuit constraints, which enables efficiency and power density improvements. Switching characteristics of the new topology are investigated and key mechanisms that control the switching process are identified. Unique analysis tools and techniques are also developed to demonstrate the application of the cascode gate drive circuit for switching performance optimisation.

A Compact Model incorporating Quantum Effects for Ultra-Thin-Body Double-Gate MOSFETs

We propose a compact model which predicts the channel charge density and the drain current which match quite closely with the numerical solution obtained from the Full-Band structure approach. We show that, with this compact model, the channel charge density can be predicted by taking the capacitance based on the physical oxide thickness, as opposed to C-eff, which needs to be taken when using the classical solution.

Behaviour of power MOSFETs at cryogenic temperatures

In this paper an investigation is reported on Siemens-power-metal-oxide-semiconductor (SIPMOS) transistors of both p and n channel types, for their suitability for cryogenic applications. The drain characteristics, temperature dependence of Rds(on) and switching behaviour have been studied in the temperature range 4.2 – 300 K in BSS91 and BSS92 MOSFETs. The experiments reveal that these types of power transistors are well suited for operations down to ≈ 30 K. However, below 30 K the operating characteristics make them unsuitable for application. This arises because of carrier freeze-out in the n− region on the substrate, which forms a drain.

A Simple Charge Model for Symmetric Double-Gate MOSFETs Adapted to Gate-Oxide-Thickness Asymmetry

Surface-potential-based compact charge models for symmetric double-gate metal-oxide-semiconductor field-effect transistors (SDG-MOSFETs) are based on the fundamental assumption of having equal oxide thicknesses for both gates. However, for practical devices, there will always be some amount of asymmetry between the gate oxide thicknesses due to process variations and uncertainties, which can affect device performance significantly. In this paper, we propose a simple surface-potential-based charge model, which is applicable for tied double-gate MOSFETs having same gate work function but could have any difference in gate oxide thickness. The proposed model utilizes the unique so-far-unexplored quasi-linear relationship between the surface potentials along the channel. In this model, the terminal charges could be computed by basic arithmetic operations from the surface potentials and applied biases, and thus, it could be implemented in any circuit simulator very easily and extendable to short-channel devices. We also propose a simple physics-based perturbation technique by which the surface potentials of an asymmetric device could be obtained just by solving the input voltage equation of SDG devices for small asymmetry cases. The proposed model, which shows excellent agreement with numerical and TCAD simulations, is implemented in a professional circuit simulator through the Verilog-A interface and demonstrated for a 101-stage ring oscillator simulation. It is also shown that the proposed model preserves the source/drain symmetry, which is essential for RF circuit design.

Threshold voltage model for accumulation mode polycrystalline SOI MOSFETs and comparisons with experimental results

In this paper, a simple but accurate semi analytical charge sheet model is presented for threshold voltage of accumulation mode polycrystalline silicon on insulator (PSOI) MOSFETs. In this model, we define the threshold voltage (V-T) of the polysilicon accumulation mode MOSFET as the gate voltage required to raise the surface potential (phi(s)) to a value phi(sT) necessary to overcome the charge trapping in the grain boundary and to create channel accumulation charge that is equal to the channel accumulation charge available in the case of single crystal silicon accumulation mode MOSFET at that phi(sT). The correctness of the model is demonstrated by comparing the theoretically estimated values of threshold voltage with the experimentally measured threshold voltages on the accumulation mode PSOI MOSFETs fabricated in the laboratory using LPCVD polysilicon layers doped with boron to achieve dopant densities in the range 3.3 x 10(-15)-5 x 10(17)/cm(3). Further, it is shown that the threshold voltage values of accumulation mode PSOI MOSFETs predicted by the present model match very closely with the experimental results, better than those obtained with the models previously reported in the literature. (C) 2012 Elsevier B.V. All rights reserved.

Nonquasi-static charge model for common double-gate MOSFETs adapted to gate oxide thickness asymmetry

With the unique quasi-linear relationship between the surface potentials along the channel, recently we have proposed a quasi-static terminal charge model for common double-gate MOSFETs, which might have asymmetric gate oxide thickness. In this brief, we extend this concept to develop the nonquasi-static (NQS) charge model for the same by solving the governing continuity equations. The proposed NQS model shows good agreement against TCAD simulations and appears to be useful for efficient circuit simulation.

Small signal Nonquasi-Static Model for Common Double-Gate MOSFETs Adapted to Gate Oxide Thickness Asymmetry

We present a physics-based closed form small signal Nonquasi-static (NQS) model for a long channel Common Double Gate MOSFET (CDG) by taking into account the asymmetry that may prevail between the gate oxide thickness. We use the unique quasi-linear relationship between the surface potentials along the channel to solve the governing continuity equation (CE) in order to develop the analytical expressions for the Y parameters. The Bessel function based solution of the CE is simplified in form of polynomials so that it could be easily implemented in any circuit simulator. The model shows good agreement with the TCAD simulation at-least till 4 times of the cut-off frequency for different device geometries and bias conditions.

Analysis of SEB and SEGR in super-junction MOSFETs

The electric field distribution in the super junction power MOSFET is analyzed using analytical modeling and numerical simulations in this paper. The single-event burn-out (SEB) and single-event gate rupture (SEGR) phenomena in this device are studied in detail. It is demonstrated that the super junction device is much less sensitive to SEB and SEGR compared to the standard power MOSFET. The physical mechanism is explained.