Parameter sensitivity for optimal design of 65 nm node SOI transistors

Mixed-mode simulation, where device simulation is embedded directly within a circuit simulator, is used for the first time to provide scaling guidelines to achieve optimal digital circuit performance for double gate SOI MOSFETs. This significant advance overcomes the lack of availability of SPICE model parameters. The sensitivity of the gate delay and on-off current ratio to each of the key geometric and technological parameters of the transistor is quantified. The impact of the source-drain doping profile on circuit performance is comprehensively investigated.

Optimisation of source/drain extension region profile for suppression of short channel effects in sub-50 nm DG SOI MOSFETs with high- k gate dielectrics

Novel technology dependent scaling parameters i.e. spacer to gradient ratio and effective channel length (Leff) are proposed for source/drain engineered DG MOSFET, and their significance in minimizing short channel effects (SCES) in high-k gate dielectrics is discussed in detail. Results show that a high-k dielectric should be associated with a higher spacer to gradient ratio to minimise SCEs The analytical model agrees with simulated data over the entire range of spacer widths, doping gradients, high-k gate dielectrics and effective channel lengths.

Performance assessment of nanoscale double- and triple- gate FinFETs

This is the first paper to describe performance assessment of triple and double gate FinFETs for High Performance (HP), Low Operating Power (LOP) and Low Standby Power (LSTP) logic technologies is investigated. The impact of gate work-function, spacer width, lateral source/drain doping gradient, fin aspect ratio, fin thickness on device performance, has been analysed in detail and guidelines are presented to meet ITRS specification at 65 and 45 nm nodes. Optimal design of lateral source/drain doping profile can not only effectively control short channel effects, yielding low off-current, but also achieve low values of intrinsic gate delay.

Thin film sputtered silicon for silicon wafer bonding applications

The transfer of functional integrated circuit layers to other substrates is being investigated for smart-sensors, MEMS, 3-D ICs and mixed semiconductor circuits. There is a need for a planarisation and bondable layer which can be deposited at low temperature and which is IC compatible. This paper describes for the first time the successful use of sputtered silicon in this role for applications as outlined above where high temperature post bond anneals are not required. It also highlights the problems of using sputtered silicon as a bonding layer in applications where post bond temperatures greater than 400C are required.

Investigation of precision grinding process for production of silicon diaphragms

The application of precision grinding for the formation of a silicon diaphragm is investigated. The test structures involved 2-6 mm diam diaphragms with thicknesses in the range of 25-150 //m. When grinding is performed without supporting the diaphragm, bending occurs due to nonuniform removal of the silicon material over the diaphragm region. The magnitude of bending depends on the µNal thickness of the diaphragm. The results demonstrate that the use of a porous silicon support can significantly reduce the amount of bending, by a factor of up to 300 in the case of 50 m thick diaphragms. The use of silicon on insulator (SOI) technology can also suppress or eliminate bending although this may be a less economical process. Stress measurements in the diaphragms were performed using x-ray and Raman spectroscopies. The results show stress of the order of 1 X107-! X108 Pa in unsupported and supported by porous silicon diaphragms while SOI technology provides stress-free diaphragms. Results obtained from finite element method analysis to determine deterioration in the performance of a 6 mm diaphragm due to bending are presented. These results show a 10% reduction in performance for a 75 µm thick diaphragm with bending amplitude of 30 fim, but negligible reduction if the bending is reduced to

Stability of Sr adatom model structures for SrTiO3(001) surface reconstructions

We report results of first-principles calculations on the thermodynamic stability of different Sr adatom structures that have been proposed to explain some of the observed reconstructions of the (001) surface of strontium titanate (Kubo and Nozoye 2003 Surf Sci. 542 177). From surface free energy calculations, a phase diagram is constructed indicating the range of conditions over which each structure is most stable. These results are compared with Kubo and Nozoye's experimental observations. It is concluded that low Sr adatom coverage structures can only be explained if the surface is far from equilibrium. Intermediate coverage structures are stable only if the surface is in or very nearly in equilibrium with the strontium oxide.

SrTiO3(001)(2x1) reconstructions: First-principles calculations of surface energy and atomic structure compared with scanning tunneling microscopy images

(1x1) and (2x1) reconstructions of the (001) SrTiO3 surface were studied using the first-principles full-potential linear muffin-tin orbital method. Surface energies were calculated as a function of TiO2 chemical potential, oxygen partial pressure and temperature. The (1x1) unreconstructed surfaces were found to be energetically stable for many of the conditions considered. Under conditions of very low oxygen partial pressure the (2x1) Ti2O3 reconstruction [Martin R. Castell, Surf. Sci. 505, 1 (2002)] is stable. The question as to why STM images of the (1x1) surfaces have not been obtained was addressed by calculating charge densities for each surface. These suggest that the (2x1) reconstructions would be easier to image than the (1x1) surfaces. The possibility that the presence of oxygen vacancies would destabilise the (1x1) surfaces was also investigated. If the (1x1) surfaces are unstable then there exists the further possibility that the (2x1) DL-TiO2 reconstruction [Natasha Erdman Nature (London) 419, 55 (2002)] is stable in a TiO2-rich environment and for p(O2)>10(-18) atm.

Electron energy-loss near-edge shape as a probe to investigate the stabilization of yttria-stabilized zirconia

The electron energy-loss near-edge structure (ELNES) at the O K edge has been studied in yttria-stabilized zirconia (YSZ). The electronic structure of YSZ for compositions between 3 and 15 mol % Y2O3 has been computed using a pseudopotential-based technique to calculate the local relaxations near the O vacancies. The results showed phase transition from the tetragonal to cubic YSZ at 10 mol % of Y2O3, reproducing experimental observations. Using the relaxed defect geometry, calculation of the ELNES was carried out using the full-potential linear muffin-tin orbital method. The results show very good agreement with the experimental O K-edge signal, demonstrating the power of using ELNES to probe the stabilization mechanism in doped metal oxides.

Free energy and molecular dynamics calculations for the cubic-tetragonal phase transition in zirconia

The high-temperature cubic-tetragonal phase transition of pure stoichiometric zirconia is studied by molecular dynamics (MD) simulations and within the framework of the Landau theory of phase transformations. The interatomic forces are calculated using an empirical, self-consistent, orthogonal tight-binding model, which includes atomic polarizabilities up to the quadrupolar level. A first set of standard MD calculations shows that, on increasing temperature, one particular vibrational frequency softens. The temperature evolution of the free-energy surfaces around the phase transition is then studied with a second set of calculations. These combine the thermodynamic integration technique with constrained MD simulations. The results seem to support the thesis of a second-order phase transition but with unusual, very anharmonic behavior above the transition temperature.