961 resultados para Diagnosi de circuits analògics
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Deep level transient spectroscopy (DLTS) technique was used to investigate deep electron states in n-type Al-doped ZnS1-xTex epilayers grown by molecular fiction epitaxy (MBE), Deep level transient Fourier spectroscopy (DLTFS) spectra of the Al-doped ZnS1-xTex (x = 0. 0.017, 0.04 and 0.046. respectively) epilayers reveal that At doping leads to the formation of two electron traps at 0.21 and 0.39 eV below the conduction hand. 1)DLTFS results suggest that in addition to the rules of Te as a component of [lie alloy as well as isoelectronic centers, Te is also involved in the formation of all electron trip, whose energy level relative to the conduction hand decreases a, Te composition increases.
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Low power design method is used in a 100MHz embedded SRAM. The embedded SRAM used in a FFT chip is divided into 16 blocks. Two-level decoders are used and only one block can be selected at one time by tristate control circuits, while other blocks are set stand-by. The SRAM cell has been optimized and the cell area has been minimized at the same time.
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We report on optoelectronic multiple chip modules, consisting of vertical cavity surface emitting laser(VCSEL), photodetector and 1.2 mum CMOS electronic circuit, The hybrid integrated components operate at a date rate of 155Mb/s, which could be used in optical interconnects for multiple computers.
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To improve the sensitivity of our laser radar system, we provided a set of control method for APDs (Avalanched Photodiodes) based on single-chip computer together with the circuits dealing with noise and temperature. It adjusts the voltages intelligently and maintains the APD's optimal working status.
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The investigations on GaAs/AlGaAs multiple quantum well self electro-optic effect device (SEED) arrays for optoelectronic smart pixels are reported. The hybrid integration of GaAs/AlGaAs multiple quantum well devices flip-chip bonding directly over 1 mu m silicon CMOS circuits are demonstrated. The GaAs/AlGaAs multiple quantum well devices are designed for 850nm operation. The measurement results under applied biases show the good optoelectronic characteristics of elements in SEED arrays. The 4x4 optoelectronic crossbar structure consisting of hybrid CMOS-SEED smart pixels have been designed, which could be potentially used in optical interconnects for multiple processors.
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A process for fabricating n channel JFET/SOS (junction field-effect transistors on silicon-on-sapphire) has been researched. The gate p(+)n junction was obtained by diffusion, and the conductive channel was gotten by a double ion implantation. Both enhancement and depletion mode transistors were fabricated in different processing conditions. From the results of the Co-50 gamma ray irradiation experimental we found that the devices had a good total dose radiation-hardness. When the tot;ll dose was 5Mrad(Si), their threshold voltages shift was less than 0.1V. The variation of transconductance and the channel leakage current were also little.
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CMOS/SOS devices have lower carriers mobility and higher channel leakage current than bulk silicon CMOS devices. These mainly results from the defects of heteroepitaxial silicon film, especially from the defects near Si-Sapphire interface. This paper describes the experiment results of CMOS/SOS devices characteristics improved by a better epitaxial silicon quality which is obtained by a modified solid phase epitaxy.
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In this paper, we investigate the effect of silicon surface cleaning prior to oxidation on the reliability of ultra-thin oxides. It is demonstrated that chemical preoxide grown in H2SO4/H2O2 (SPM) solution prior to oxidation provides better oxide integrity than both HF-based solution dipping and preoxide grown in RCA SC1 or SC2 solutions. It is also found that the oxides with SPM preoxide exhibit better hot-carrier immunity than the RCA cleaned oxides.
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In this paper a new half-flash architecture for high speed video ADC is presented. Based on a high speed single-way analog switch circuit, this architecture effectively reduces the number of elements. At the same lime no sacrifice of speed is needed compared with the normal half-flash structure.
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In this paper we introduce a new Half-flash analog switch ADC architecture. And we discuss two methods to design the values of the cascaded resistors which generate the reference voltages. Derailed analysis about the effect of analog switches and comparators on reference voltages, and the methods to set the resistor values and correspond;ng voltage errors are given.
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This paper introduces a new highspeed single-way analog switch which has both highspeed high-resolution mono-direction analog transmission gate function and high-speed digital logic gate function with normal bipolar technology. The analysis of static and transient switching performances as an analog transmission gate is emphasized in the paper. In order to reduce the plug-in effect on high-speed high-resolution systems, an optimum design scheme is also given. This scheme is to achieve accelerated dynamic response with very low bias power dissipation. The analysis of PSPICE simulation as well as the circuit test results confirms the feasibility of the scheme. Now, the circuit has been applied effectively to the designs of novel highspeed A/D and D/A converters.
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In this paper, a one-way NMOS analog switch featuring a low plug-in consumption is presented. The performances of analog switch, especially the performances of source follower are simulated under different conditions with PSPICE. Simulation results and factors affecting the deviation between input and output are analyzed, some advice on how to reduce the deviation between input and output is given. Ar the end of the paper, voltage relationship between input and output of the analog switch is obtained. Function of first degree, Vout = kVin + V0, is used to approximate the voltage relationship. The simulation results anti the value achieved from the approximation equation are given as well.
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Self-organized InAs quantum; dots sheets are grown on GaAs(100) substrate and tapped by 80nm GaAs layer with molecular beam epitaxy. Samples were annealed and characterized with Raman spectra, transmission electron microscopy (TEM) and photolumincscence (PL). The Raman spectra indicates arsenic clusters in the GaAs capping layer. The TEM analysis revealed the relaxation of strain in some InAs islands with the introduction of the network of 90 dislocations. In addition, the structural changes also lead to the changes of the PL spectra from me InAs islands. Their correlation was discussed, Our results suggest:est that annealing may be used to intentionally modify me properties of self-organized InAs islands on GaAs.
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This paper presents a detailed PL study of Fe2+ related four zero-phonon(ZP) lines and their related phonon sidebands. Four zero-phonon transitions at approximate to 2800 cm(-1) along with the accompanying phonon sidebands extending down to 2400 cm(-1). There are ta two prominent regions in the phonon sidebands. One is ascribed to coupling to acoustic-type phonons (2700 cm(-1) region), the other is due to coupling to optic-type phonons (2500 cm(-1) region). Beside broad coupling with lattice modes, there are several groups of lines. They are ascribed to resonant modes, impurities induced gap modes and local modes.