Influence of growth parameters of frequency-radio plasma nitrogen source on extending emission wavelengths from 1.31 mu m to 1.55 mu m GaInNAs/GaAs quantum wells grown by molecular-beam epitaxy

High (42.5%) indium content GaInNAs/GaAs quantum wells with room temperature emission wavelength from 1.3 mu m to 1.5 mu m range were successfully grown by Radio Frequency Plasma Nitrogen source assisted Molecular Beam Epitaxy. The growth parameters of plasma power and N-2 How rate were optimized systematically to improve the material quality. Photoluminescence and transmission electron microscopy measurements showed that the optical and crystal quality of the 1.54 mu m GaInNAs/GaAs QWs was kept as comparable as that in 1.31 mu m.

High-quality GaN grown by gas-source MBE

High-quality GaN epilayers were consistently obtained using a home-made gas-sourer MBE system on sapphire substrates. Room-temperature electron mobility of the grown GaN film is 300 cm(2)/V s with a background electron concentration as low as 2 x 10(17) cm(-3) The full-width at half-maximum of the GaN (0 0 0 2) double-crystal X-ray rocking curve is 6 arcmin. At low temperature (3.5 K), the FWHM of the: near-band-edge photoluminescence emission line is 10 meV. Furthermore, using piezoelectric effect alone with the high-quality films, two-dimensional electron gas was formed in a GaN/AlN/GaN/sapphire structure. Its room-temperature and low-temperature (77 K) electron mobility is 680 cm(2)/V s and 1700 cm(2)/V s, and the corresponding sheet electron density is 3.2 x 10(13) and 2.6 x 10(13) cm(-2), respectively. (C) 2001 Published by Elsevier Science.

Self-assembled GaAs quantum rings by MBE droplet epitaxy

Fabrication of semiconductor nanostructures such as quantum dots (QDs), quantum rings (QRs) has been considered as the important step for realization of solid state quantum information devices, including QDs single photon emission source, QRs single electron memory unit, etc. To fabricate GaAs quantum rings, we use Molecular Beam Epitaxy (MBE) droplet technique in this report. In this droplet technique, Gallium (Ga) molecular beams are supplied initially without Arsenic (As) ambience, forming droplet-like nano-clusters of Ga atoms on the substrate, then the Arsenic beams are supplied to crystallize the Ga droplets into GaAs crystals. Because the morphologies and dimensions of the GaAs crystal are governed by the interplay between the surface migration of Ga and As adatoms and their crystallization, the shape of the GaAs crystals can be modified into rings, and the size and density can be controlled by varying the growth temperatures and As/Ga flux beam equivalent pressures(BEPs). It has been shown by Atomic force microscope (AFM) measurements that GaAs single rings, concentric double rings and coupled double rings are grown successfully at typical growth temperatures of 200 C to 300 C under As flux (BEP) of about 1.0 x 10(-6) Torr. The diameter of GaAs rings is about 30-50 nm and thickness several nm.

QUANTITATIVE-ANALYSIS OF INXGA1-XAS BY AUGER-ELECTRON SPECTROSCOPY

Quantitative Auger electron spectroscopy analysis for the ternary system InGa1-xAs grown by molecular-beam epitaxy has been studied. The relative sensitivity factors are determined by with an internal reference element. The matrix correction factor for In relative to Ga was shown to be 1.08. No preferential sputtering of As for the ternary compounds was found, and the sputter correction factor, K(s)InGa is 0.75. The results are compared with that measured by the x-ray double-crystal diffraction analysis, electron probe microanalysis, and Auger analysis without matrix and sputter corrections.

Detection of Terahertz Photon by GaAs-Based Single Electron Transistor at Low Temperatures

A reproducible terahertz (THz) photocurrent was observed at low temperatures in a Schottky wrap gate single electron transistor with a normal-incident of a CH_3OH gas laser with the frequency 2. 54THz.The change of source-drain current induced by THz photons shows that a satellite peak is generated beside the resonance peak. THz photon energy can be characterized by the difference of gate voltage positions between the resonance peak and satellite peak. This indicates that the satellite peak exactly results from the THz photon-assisted tunneling. Both experimental results and theoretical analysis show that a narrow spacing of double barriers is more effective for the enhancement of THz response.

Observation of deep electron states in n-type Al-doped ZnS1-xTex grown by molecular beam epitaxy

Deep level transient spectroscopy (DLTS) technique was used to investigate deep electron states in n-type Al-doped ZnS1-xTex epilayers grown by molecular fiction epitaxy (MBE), Deep level transient Fourier spectroscopy (DLTFS) spectra of the Al-doped ZnS1-xTex (x = 0. 0.017, 0.04 and 0.046. respectively) epilayers reveal that At doping leads to the formation of two electron traps at 0.21 and 0.39 eV below the conduction hand. 1)DLTFS results suggest that in addition to the rules of Te as a component of [lie alloy as well as isoelectronic centers, Te is also involved in the formation of all electron trip, whose energy level relative to the conduction hand decreases a, Te composition increases.

High-quality GaN grown by gas-source MBE

High-quality GaN epilayers were consistently obtained using a home-made gas-sourer MBE system on sapphire substrates. Room-temperature electron mobility of the grown GaN film is 300 cm(2)/V s with a background electron concentration as low as 2 x 10(17) cm(-3) The full-width at half-maximum of the GaN (0 0 0 2) double-crystal X-ray rocking curve is 6 arcmin. At low temperature (3.5 K), the FWHM of the: near-band-edge photoluminescence emission line is 10 meV. Furthermore, using piezoelectric effect alone with the high-quality films, two-dimensional electron gas was formed in a GaN/AlN/GaN/sapphire structure. Its room-temperature and low-temperature (77 K) electron mobility is 680 cm(2)/V s and 1700 cm(2)/V s, and the corresponding sheet electron density is 3.2 x 10(13) and 2.6 x 10(13) cm(-2), respectively. (C) 2001 Published by Elsevier Science.

Advanced superconducting electron cyclotron resonance ion source SECRAL: Design, construction, and the first test result

Superconducting electron cyclotron resonance (ECR) ion source with advanced design in Lanzhou (SECRAL) is a next generation ECR ion source and aims for developing a very compact superconducting ECR ion source with a structure and high performances for highly charged ion-beam production. The ion source was designed to be operated at 18 GHz at initial operation and finally will be extended to 28 GHz. The superconducting magnet confinement configuration of the ion source consists of three axial solenoid coils and six sextupole coils with a cold iron structure as field booster and clamping. At full excitation, this magnet assembly can produce peak mirror fields on the axis of 3.6 T at injection, 2.2 T at extraction, and a radial sextupole field of 2.0 T at plasma chamber wall. What is different from the traditional design, such as LBNL VENUS and LNS SERSE, is that the three axial solenoid coils are located inside of the sextupole bore in order to reduce the interaction forces between the sextupole coils and the solenoid coils. SECRAL may open the way for building a compact and high-performance 18-28 GHz superconducting ECR ion source. Very preliminary commissioning results are promising. Detailed design, construction issues and very preliminary test results of the ion source at 18 GHz are presented.

Beam-target double-spin asymmetry A{LT} in charged pion production from deep inelastic scattering on a transversely polarized {3}He target at 1.4

We report the first measurement of the double-spin asymmetry A{LT} for charged pion electroproduction in semi-inclusive deep-inelastic electron scattering on a transversely polarized {3}He target. The kinematics focused on the valence quark region, 0.16

Microcontroller based double beam modulation system for atomic scattering experiments

Double beam modulation is widely used in atomic collision experiments in the case where the noise arising froth each of the beams exceeds the measured signal. A method for minimizing the statistical uncertainty in a measured signal in a given time period is discussed, and a flexible modulation and counting system based on a low cost PIC microcontroller is described. This device is capable of modifying the acquisition parameters in real time during the course of an experimental run. It is shown that typical savings in data acquisition time of approximately 30% can be achieved using this optimized modulation scheme.

6-T SRAM cell design with nanoscale double-gate SOI MOSFETs: impact of source/drain engineering and circuit topology

The impact of source/drain engineering on the performance of a six-transistor (6-T) static random access memory (SRAM) cell, based on 22 nm double-gate (DG) SOI MOSFETs, has been analyzed using mixed-mode simulation, for three different circuit topologies for low voltage operation. The trade-offs associated with the various conflicting requirements relating to read/write/standby operations have been evaluated comprehensively in terms of eight performance metrics, namely retention noise margin, static noise margin, static voltage/current noise margin, write-ability current, write trip voltage/current and leakage current. Optimal design parameters with gate-underlap architecture have been identified to enhance the overall SRAM performance, and the influence of parasitic source/drain resistance and supply voltage scaling has been investigated. A gate-underlap device designed with a spacer-to-straggle (s/sigma) ratio in the range 2-3 yields improved SRAM performance metrics, regardless of circuit topology. An optimal two word-line double-gate SOI 6-T SRAM cell design exhibits a high SNM similar to 162 mV, I-wr similar to 35 mu A and low I-leak similar to 70 pA at V-DD = 0.6 V, while maintaining SNM similar to 30% V-DD over the supply voltage (V-DD) range of 0.4-0.9 V.

Performance projections and design optimization of planar double gate SOI MOSFETs for logic technology applications

In this paper, by investigating the influence of source/drain extension region engineering (also known as gate-source/drain underlap) in nanoscale planar double gate (DG) SOI MOSFETs, we offer new insights into the design of future nanoscale gate-underlap DG devices to achieve ITRS projections for high performance (HP), low standby power (LSTP) and low operating power (LOP) logic technologies. The impact of high-kappa gate dielectric, silicon film thickness, together with parameters associated with the lateral source/drain doping profile, is investigated in detail. The results show that spacer width along with lateral straggle can not only effectively control short-channel effects, thus presenting low off-current in a gate underlap device, but can also be optimized to achieve lower intrinsic delay and higher on-off current ratio (I-on/I-off). Based on the investigation of on-current (I-on), off-current (I-off), I-on/I-off, intrinsic delay (tau), energy delay product and static power dissipation, we present design guidelines to select key device parameters to achieve ITRS projections. Using nominal gate lengths for different technologies, as recommended from ITRS specification, optimally designed gate-underlap DG MOSFETs with a spacer-to-straggle (s/sigma) ratio of 2.3 for HP/LOP and 3.2 for LSTP logic technologies will meet ITRS projection. However, a relatively narrow range of lateral straggle lying between 7 to 8 nm is recommended. A sensitivity analysis of intrinsic delay, on-current and off-current to important parameters allows a comparative analysis of the various design options and shows that gate workfunction appears to be the most crucial parameter in the design of DG devices for all three technologies. The impact of back gate misalignment on I-on, I-off and tau is also investigated for optimized underlap devices.

Engineering source/drain extension regions in nanoscale double gate (DG) SOI MOSFETs: Analytical model and design considerations

In this paper, we propose for the first time, an analytical model for short channel effects in nanoscale source/drain extension region engineered double gate (DG) SOI MOSFETs. The impact of (i) lateral source/drain doping gradient (d), (ii) spacer width (s), (iii) spacer to doping gradient ratio (s/d) and (iv) silicon film thickness (T-si), on short channel effects - threshold voltage (V-th) and subthreshold slope (S), on-current (I-on), off-current (I-on) and I-on/I-off is extensively analysed by using the analytical model and 2D device simulations. The results of the analytical model confirm well with simulated data over the entire range of spacer widths, doping gradients and effective channel lengths. Results show that lateral source/drain doping gradient along with spacer width can not only effectively control short channel effects, thus presenting low off-current, but can also be optimised to achieve high values of on-currents. The present work provides valuable design insights in the performance of nanoscale DG Sol devices with optimal source/drain engineering and serves as a tool to optimise important device and technological parameters for 65 nm technology node and below. (c) 2006 Elsevier Ltd. All rights reserved.