965 resultados para Chip


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This paper proposes an embedded ultra low power nonvolatile memory in a standard CMOS logic process. The memory adopts a bit cell based on the differential floating gate PMOS structure and a novel operating scheme. It can greatly improve the endurance and retention characteristic and make the area/bit smaller. A new high efficiency all-PMOS charge pump is designed to reduce the power consumption and to increase the power efficiency. It eliminates the body effect and can generate higher output voltage than conventional structures for a same stage number. A 32-bit prototype chip is fabricated in a 0.18 mu m 1P4M standard CMOS logic process and the core area is 0.06 mm(2). The measured results indicate that the typical write/erase time is 10ms. With a 700 kHz clock frequency, power consumption of the whole memory is 2.3 mu A for program and 1.2 mu A for read at a 1.6V power supply.

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A low-cost low-power single chip WLAN 802.11a transceiver is designed for personal communication terminal and local multimedia data transmission. It has less than 130mA current dissipation, maximal 67dB gain and can be programmed to be 20dB minimal gain. The receiver system noise figure is 6.4dB in hige-gain mode.

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In this paper, a wide-band low noise amplifier, two mixers and a VCO with its buffers implemented in 50GHz 0.35 mu m SiGe BiCMOS technology for dual-conversion digital TV tuner front-end is presented. The LNA and up-converting mixer utilizes current injection technology to achieve high linearity. Without using inductors, the LNA achieves 0.1-1GHz wide bandwidth and 18.8-dB gain with less than 1.4-dB gain variation. The noise figure of the LNA is less than 5dB and its 1dB compression point is -2 dBm. The IIP3 of two mixers is 25-dBm. The measurement results show that the VCO has -127.27-dBc/Hz phase noise at 1-MHz offset and a linear gain of 32.4-MHz/V between 990-MHz and 1.14-GHz. The whole chip consume 253mW power with 5-V supply.

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The prototype wafer of a low power integrated CMOS Transmitter for short-range biotelemetry application has been designed and fabricated, which is prospective to be implanted in the human brain to transfer the extracted neural information to the external computer. The transmitter consists of five parts, a bandgap current regulator, a ring oscillator, a buffer, a modulator and a power transistor. High integration and low power are the most distinct criteria for such an implantable integrated circuit. The post-simulation results show that under a 3.3 V power supply the transmitter provides 100.1 MHz half-wave sinusoid current signal to drive the off-chip antenna, the output peak current range is -0.155 mA similar to 1.250 mA, and on-chip static power dissipation is low to 0.374 mW. All the performances of the transmitter satisfy the demands of wireless real-time BCI system for neural signals recording and processing.

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This paper presents a low-voltage, high performance charge pump circuit suitable for implementation in standard CMOS technologies. The proposed charge pump has been used as a part of the power supply section of fully integrated passive radio frequency identification(RFID) transponder IC, which has been implemented in a 0.35-um CMOS technology with embedded EEPROM offered by Chartered Semiconductor. The proposed DC/DC charge pump can generate stable output for RFID applications with low power dissipation and high pumping efficiency. The analytical model of the voltage multiplier, the comparison with other charge pumps, the simulation results, and the chip testing results are presented.

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Width varied quantum wells show a more flat and wide gain spectrume (about 115nm) than that of identical miltiple quantum well. A new fabricating method was demonstrated in this paper to realize two different Bragg grating in an selectable DFB laser based on this material grown identical chip using traditional holographic exposure. A wavelength by MOVPE was presented. Two stable distinct single longitudinal mode of 1510nm and 1530nm with SMSR of 45 dB were realized.

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A novel microwave packaging technique for 10Gb/s electro-absorption modulator integrated with distributed feedback laser (EML) is presented. The packaging parasitics and intrinsic parasitics are both well considered, and the packaging circuit was synthetically designed to compensate for the intrinsic parasitic of the chip. A butterfly-packaged EMI module has been successfully developed to prove that. The small-signal modulation bandwidth of the butterfly-packaged module is about 10 GHz. Optical fiber transmission experiments have shown that the module can be used for 10Gb/s optical transmission system. After transmission through 40km,. the power penalty is less than 1 dBm at a bit-error-rate of 10-12.

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An extended subtraction method of scattering parameters for characterizing laser diode is introduced in this paper. The intrinsic small-signal response can be directly extracted from the measured transmission coefficients of laser diode by the method. However the chip temperature may change with the injection bias current due to thermal effects, which causes inaccurate intrinsic response by our method. Therefore, how to determine the chip temperature and keep the laser chip adiabatic is very critical when extracting the intrinsic response. To tackle these problems, the dependence of the lasing wavelength of the laser diode on the chip temperature is investigated, and an applicable measurement setup which keeps the chip temperature stable is presented. The scattering parameters of laser diode are measured on diabatic and adiabatic conditions, and the extracted intrinsic responses for both conditions are compared. It is found that the adiabatic intrinsic responses are evidently superior to those without thermal consideration. The analysis indicates that inclusion of thermal effects is necessary to acquire accurate intrinsic response.

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Optoelectronic packaging has become a most important factor that influences the final performance and cost of the module. In this paper, low microwave loss coplanar waveguide(CPW) on high resistivity silicon(HRS) and precise V groove in silicon substrate were successfully fabricated. The microwave attenuation of the CPW made on HRS with the simple process is lower than 2 dB/cm in the frequency range of 0 similar to 26GHz, and V groove has the accuracy in micro level and smooth surface. These two techniques built a good foundation for high frequency packaging and passive coupling of the optoelectronic devices. Based on these two techniques, a simple high resistivity silicon substrate that integrated V groove and CPW for flip-chip packaging of lasers was completed. It set a good example for more complicate optoelectronic packaging.

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This paper proposes a novel, fast lock-in, phase-locked loop (PLL) frequency synthesizer. The synthesizer includes a novel mixed-signal voltage-controlled oscillator (VCO) with a direct frequency presetting circuit. The frequency presetting circuit can greatly speed up the lock-in process by accurately the presetting oscillation frequency of the VCO. We fully integrated the synthesizer in standard 0.35 mu m, 3.3 V complementary metal-oxide-semiconductors (CMOS) process. The entire chip area is only 0.4 mm(2). The measured results demonstrate that the synthesizer can speed up the lock-in process significantly and the lock-in time is less than 10 mu s over the entire oscillation frequency range. The measured phase noise of the synthesizer is -85 dBc/Hz at 10 kHz offset. The synthesizer avoids the tradeoff between the lock-in speed and the phase noise/spurs. The synthesizer monitors the chip temperature and automatically compensates for the variation in frequency with temperature.

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This paper describes the design process and performance of the optimized parallel optical transmission module. Based on 1x12 VCSEL (Vertical Cavity Surface Emitting Laser) array, we designed and fabricated the high speed parallel optical modules. Our parallel optical module contains a 1x12 VCSEL array, a 12 channel CMOS laser driver circuit, a high speed PCB (Printed Circuit Board), a MT fiber connector and a packaging housing. The L-I-V characteristics of the 850nm VCSEL was measured at the operating current 8mA, 3dB frequency bandwidth more than 3GHz and the optical output 1mW. The transmission rate of all 12 channels is 30Gbit/s, with a single channel 2.5Gbit/s. By adopting the integration of the 1x12 VCSEL array and the driver array, we make a high speed PCB (Printed Circuit Board) to provide the optoelectronic chip with the operating voltage and high speed signals current. The LVDS (Low-Voltage Differential Signals) was set as the input signal to achieve better high frequency performance. The active coupling was adopted with a MT connector (8 degrees slant fiber array). We used the Small Form Factor Pluggable (SFP) packaging. With the edge connector, the module could be inserted into the system dispense with bonding process.

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The present study reports a subretinal implant device which can imitate the function of photoreceptor cells. Photodiode (PD) arrays on the chip translate the incident light into current according to the intensity of light. With an electrode at the end of every photodiode, the PDs transfer the current to the remnant healthy visual cells such as bipolar cells and horizontal cells and then activate these cells. Biocompatible character of the materials and artificial photoreceptor itself were tested and the photoelectric characteristics of the chips in simulative condition were described and discussed.

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This paper proposes a smart frequency presetting technique for fast lock-in LC-PLL frequency synthesizer. The technique accurately presets the frequency of VCO with small initial frequency error and greatly reduces the lock-in time. It can automatically compensate preset frequency variation with process and temperature. A 2.4GHz synthesizer with 1MHz reference input was implemented in 0.35 mu m CMOS process. The chip core area is 0.4mm(2). Output frequency of VCO ranges from 2390 to 2600MHz. The measured results show that the typical lock-in time is 3 mu s. The phase noise is -112dBc/Hz at 600KHz offset from center frequency. The test chip consumes current of 22mA that includes the consumption of the I/O buffers.

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We investigate the dispersion properties of nanometer-scaled silicon waveguides with channel and rib cross section around the optical fiber communication wavelength and systematically study their relationship with the key structural parameters of the waveguide. The simulation results show that the introduction of an extra degree of freedom in the rib depth enables the rib waveguide more flexible in engineering the group velocity dispersion (GVD) compared with the channel waveguide. Besides, we get the structural parameters of the waveguides that can realize zero-GVD at 1550 nm.

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We report on chip-scale optical gates based on the integration of evanescent waveguide unitraveling-carrier photodiodes (EC-UTC-PDs) and intra-step quantum well electroabsorption modulators (IQW-EAMs) on n-InP substrates. These devices exhibit simultaneously 2.1 GHz and -16.2 dB RF-gain at 21 GHz with a 450 Omega thin-film resistor and a bypass capacitor integrated on a chip.