A Smart Frequency Presetting Technique for Fast Lock-in LC-PLL Frequency Synthesizer

This paper proposes a smart frequency presetting technique for fast lock-in LC-PLL frequency synthesizer. The technique accurately presets the frequency of VCO with small initial frequency error and greatly reduces the lock-in time. It can automatically compensate preset frequency variation with process and temperature. A 2.4GHz synthesizer with 1MHz reference input was implemented in 0.35 mu m CMOS process. The chip core area is 0.4mm(2). Output frequency of VCO ranges from 2390 to 2600MHz. The measured results show that the typical lock-in time is 3 mu s. The phase noise is -112dBc/Hz at 600KHz offset from center frequency. The test chip consumes current of 22mA that includes the consumption of the I/O buffers.

Submitted by 阎军 (yanj@red.semi.ac.cn) on 2010-04-26T16:11:00Z No. of bitstreams: 1 A Smart Frequency Presetting Technique for Fast Lock-in LC-PLL Frequency Synthesizer.pdf: 1164798 bytes, checksum: 177f0d3bb02ca9fafd3072f16103e7ba (MD5)

Made available in DSpace on 2010-04-26T16:11:00Z (GMT). No. of bitstreams: 1 A Smart Frequency Presetting Technique for Fast Lock-in LC-PLL Frequency Synthesizer.pdf: 1164798 bytes, checksum: 177f0d3bb02ca9fafd3072f16103e7ba (MD5) Previous issue date: 2009

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