A novel fast lock-in phase-locked loop frequency synthesizer with direct frequency presetting circuit
Data(s) |
2006
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Resumo |
This paper proposes a novel, fast lock-in, phase-locked loop (PLL) frequency synthesizer. The synthesizer includes a novel mixed-signal voltage-controlled oscillator (VCO) with a direct frequency presetting circuit. The frequency presetting circuit can greatly speed up the lock-in process by accurately the presetting oscillation frequency of the VCO. We fully integrated the synthesizer in standard 0.35 mu m, 3.3 V complementary metal-oxide-semiconductors (CMOS) process. The entire chip area is only 0.4 mm(2). The measured results demonstrate that the synthesizer can speed up the lock-in process significantly and the lock-in time is less than 10 mu s over the entire oscillation frequency range. The measured phase noise of the synthesizer is -85 dBc/Hz at 10 kHz offset. The synthesizer avoids the tradeoff between the lock-in speed and the phase noise/spurs. The synthesizer monitors the chip temperature and automatically compensates for the variation in frequency with temperature. This paper proposes a novel, fast lock-in, phase-locked loop (PLL) frequency synthesizer. The synthesizer includes a novel mixed-signal voltage-controlled oscillator (VCO) with a direct frequency presetting circuit. The frequency presetting circuit can greatly speed up the lock-in process by accurately the presetting oscillation frequency of the VCO. We fully integrated the synthesizer in standard 0.35 mu m, 3.3 V complementary metal-oxide-semiconductors (CMOS) process. The entire chip area is only 0.4 mm(2). The measured results demonstrate that the synthesizer can speed up the lock-in process significantly and the lock-in time is less than 10 mu s over the entire oscillation frequency range. The measured phase noise of the synthesizer is -85 dBc/Hz at 10 kHz offset. The synthesizer avoids the tradeoff between the lock-in speed and the phase noise/spurs. The synthesizer monitors the chip temperature and automatically compensates for the variation in frequency with temperature. zhangdi于2010-03-29批量导入 zhangdi于2010-03-29批量导入 Japan Soc Appl Phys & Tech.; IEEE Elect Devices Soc. Chinese Acad Sci, Inst Semicond, State Key Lab Superlattices & Microstruct, Beijing 100083, Peoples R China; Liuhewantong Microelect Ltd, Beijing 100085, Peoples R China Japan Soc Appl Phys & Tech.; IEEE Elect Devices Soc. |
Identificador | |
Idioma(s) |
英语 |
Publicador |
INST PURE APPLIED PHYSICS 5F YUSHIMA BLDG, 2-31-22 YUSHIMA, BUNKYO-KU, TOKYO, 113-0034, JAPAN |
Fonte |
Kuang, XF; Wu, NJ; Shou, GL .A novel fast lock-in phase-locked loop frequency synthesizer with direct frequency presetting circuit .见:INST PURE APPLIED PHYSICS .JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS,5F YUSHIMA BLDG, 2-31-22 YUSHIMA, BUNKYO-KU, TOKYO, 113-0034, JAPAN ,APR 2006,45 (4B): 3290-3294 |
Palavras-Chave | #半导体物理 #lock-in speed |
Tipo |
会议论文 |