990 resultados para Speed limits


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This paper describes a 12-bit 300 MHz CMOS DAC for high-speed system applications. The proposed DAC consists of a unit current-cell matrix for 8 MSBs and a binary-weighted array for 4 LSBs. In order to ensure the linearity of DAC, a double Centro symmetric current matrix is designed by using the Q(2) random walk strategy. To minimize the feedthrough and improve the dynamic performance, the drain of the switching transistors is isolated from the output lines by adding two cascoded transistors.

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An ultra-wide-band frequency response measurement system for optoelectronic devices has been established using the optical heterodyne method utilizing a tunable laser and a wavelenath-fixed distributed feedback laser. By controlling the laser diode cavity length, the beat frequency is swept from DC to hundreds GHz. An outstanding advantage is that this measurement system does not need any high-speed light modulation source and additional calibration. In this measurement, two types of different O/E receivers have been tested. and 3 dB bandwidths measured by this system were 14.4GHz and 40GHz, respectively. The comparisons between experimental data and that from manufacturer show that this method is accurate and easy to carry out.

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In this paper.. the status and limits in the development of the silicon microelectronics industry are presented briefly. The key countermeasures given are use of the new structure materials and the new device structures.

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This paper presents measurement methods for determining the reflection coefficients and frequency responses of semiconductor laser diodes, photodiodes, and EA modulator chips. A novel method for determining the intrinsic frequency responses of laser diodes is also proposed, and applications of the developed measurement methods are discussed. We demonstrate the compensation of bonding wire on the capacitances of both the submount and the laser diode, and present a method for estimating the potential modulation bandwidth of TO packaging technique. Initial study on removing the effects of test fixture on large-signal performances of optoelectronic devices at high data rate is also given.

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Although the monophyly of Chiroptera is well supported by many independent studies, higher-level systematics, e.g. the monophyly of microbats, remains disputed by morphological and molecular studies. Chromosomal rearrangements, as one type of rare genomic changes, have become increasingly popular in phylogenetic studies as alternatives to molecular and other morphological characters. Here, the representatives of families Megadermatidae and Emballonuridae are studied by comparative chromosome painting for the first time. The results have been integrated into published comparative maps, providing an opportunity to assess genome-wide chromosomal homologies between the representatives of eight bat families. Our results further substantiate the wide occurrence of Robertsonian translocations in bats, with the possible involvement of whole-arm reciprocal translocations (WARTs). In order to search for valid cytogenetic signature(s) for each family and superfamily, evolutionary chromosomal rearrangements identified by chromosomal painting and/or banding comparison are subjected to two independent analyses: (1) a cladistic analysis using parsimony and (2) the mapping of these chromosomal changes onto the molecularly defined phylogenetic tree available fromthe literature. Both analyses clearly indicate the prevalence of homoplasic events that reduce the reliability of chromosomal characters for resolving interfamily relationships in bats.

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Ge-on-silicon-on-insulator p-i-n photodetectors were fabricated using an ultralow-temperature Ge buffer by ultrahigh-vacuum chemical vapor deposition. For a detector of 70-mu m diameter, the 1-dB small-signal compression power was about 110.5 mW. The 3-dB bandwidth at 3-V reverse bias was 13.4 GHz.

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This paper presents a high speed ROM-less direct digital frequency synthesizer (DDFS) which has a phase resolution of 32 bits and a magnitude resolution of 10 bits. A 10-bit nonlinear segmented DAC is used in place of the ROM look-up table for phase-to-sine amplitude conversion and the linear DAC in a conventional DDFS.The design procedure for implementing the nonlinear DAC is presented. To ensure high speed, current mode logic (CML) is used. The chip is implemented in Chartered 0.35μm COMS technology with active area of 2.0 × 2.5 mm~2 and total power consumption of 400 mW at a single 3.3 V supply voltage. The maximum operating frequency is 850 MHz at room temperature and 1.0 GHz at 0 ℃.

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Silicon-based high-speed electro-optical modulator is the key component of silicon photonics for future communiction and interconnection systems. In this paper, introduced are the optical mudulation mechanisms in silicon, reviewed are some recent progresses in high-speed silicon modulators, and analyzed are advantages and shortages of the silicon modulators of different types.

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The design and fabrication of a high speed, 12-channel monolithic integrated CMOS optoelectronic integrated circuit(OEIC) receiver are reported.Each channel of the receiver consists of a photodetector,a transimpedance amplifier,and a post-amplifier.The double photodiode structure speeds up the receiver but hinders responsivity.The adoption of active inductors in the TIA circuit extends the-3dB bandwidth to a higher level.The receiver has been realized in a CSMC 0.6μm standard CMOS process.The measured results show that a single channel of the receiver is able to work at bit rates of 0.8~1.4Gb/s. Altogether, the 12-channel OEIC receiver chip can be operated at 15Gb/s.

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A high performance AlAs/In0.53 Ga0.47 As/InAs resonant tunneling diode (RTD) on InP substrate is fabricated by inductively coupled plasma etching. This RTD has a peak-to-valley current ratio (PVCR) of 7. 57 and a peak current density Jp = 39.08kA/cm^2 under forward bias at room temperature. Under reverse bias, the corresponding values are 7.93 and 34.56kA/cm^2 . A resistive cutoff frequency of 18.75GHz is obtained with the effect of a parasitic probe pad and wire. The slightly asymmetrical current-voltage characteristics with a nominally symmetrical structure are also discussed.

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Design and fabrication of a parallel optical transmitter are reported. The optimized 12 channel parallel optical transmitter,with each channel's data rate up to 3Gbit/s,is designed, assembled, and measured. A top-emitting 850nm vertical cavity surface emitting laser(VCSEL) array is adopted as the light source,and the VCSEL chip is directly wire bonded to a 12 channel driver IC. The outputs of the VCSEL array are directly butt coupled into a 12 channel fiber array. Small form factor pluggable (SFP) packaging technology is used in the module to support hot pluggable in application. The performance results of the module are demonstrated. At an operating current of 8mA, an eye diagram at 3Gbit/s is achieved with an optical output of more than 1mW.

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In this paper, we present simulation results of an electrooptical variable optical attenuator (VOA) inte-grated in silicon-on-insulator waveguide. The device is functionally based on free carriers absorption toachieve attenuation. Beam propagation method (BPM) and two-dimensional semiconductor device simu-lation tool PISCES-Ⅱ were used to analyze the dc and transient characteristics of the device. The devicehas a response time (including rise time and fall time) less than 200 ns, much faster than the thermoopticand micro-electromechanical systems (MEMSs) based VOAs.