A 12-bit 300 MHz CMOS DAC for high-speed system applications

This paper describes a 12-bit 300 MHz CMOS DAC for high-speed system applications. The proposed DAC consists of a unit current-cell matrix for 8 MSBs and a binary-weighted array for 4 LSBs. In order to ensure the linearity of DAC, a double Centro symmetric current matrix is designed by using the Q(2) random walk strategy. To minimize the feedthrough and improve the dynamic performance, the drain of the switching transistors is isolated from the output lines by adding two cascoded transistors.

This paper describes a 12-bit 300 MHz CMOS DAC for high-speed system applications. The proposed DAC consists of a unit current-cell matrix for 8 MSBs and a binary-weighted array for 4 LSBs. In order to ensure the linearity of DAC, a double Centro symmetric current matrix is designed by using the Q(2) random walk strategy. To minimize the feedthrough and improve the dynamic performance, the drain of the switching transistors is isolated from the output lines by adding two cascoded transistors.

zhangdi于2010-03-29批量导入

Made available in DSpace on 2010-03-29T06:06:11Z (GMT). No. of bitstreams: 1 2280.pdf: 3076632 bytes, checksum: 1c62881ca17557a67731cfbaaa9dea3d (MD5) Previous issue date: 2006

IEEE.

Chinese Acad Sci, Inst Semiconductors, Beijing 100083, Peoples R China; Auburn Univ, Dept Elect & Comp Engn, Auburn, AL 36849 USA

IEEE.