A versatile content addressable memory architecture

In this paper, a novel configurable content addressable memory (CCAM) cell is proposed, to increase the flexibility of embedded CAMs for SoC employment. It can be easily configured as a Binary CAM (BiCAM) or Ternary CAM (TCAM) without significant penalty of power consumption or searching speed. A 64x128 CCAM array has been built and verified through simulation. ©2007 IEEE.

A VLSI architecture for multiplication, division and square root

A high-performance VLSI architecture to perform combined multiply-accumulate, divide, and square root operations is proposed. The circuit is highly regular, requires only minimal control, and can be reconfigured for every cycle. The execution time for each operation is the same. The combination of redundancy and pipelining results in a throughput independent of the wordsize of the array. With current CMOS technology, throughput rates in excess of 80 million operations per second are achievable.

High performance VLSI architecture for Wave Digital Filtering

The application of fine grain pipelining techniques in the design of high performance Wave Digital Filters (WDFs) is described. It is shown that significant increases in the sampling rate of bit parallel circuits can be achieved using most significant bit (msb) first arithmetic. A novel VLSI architecture for implementing two-port adaptor circuits is described which embodies these ideas. The circuit in question is highly regular, uses msb first arithmetic and is implemented using simple carry-save adders. © 1992 Kluwer Academic Publishers.

Bit-level systolic architecture for very high performance IIR filters

A novel bit-level systolic array architecture for implementing bit-parallel IIR filter sections is presented. The authors have shown previously how the fundamental obstacle of pipeline latency in recursive structures can be overcome by the use of redundant arithmetic in combination with bit-level feedback. These ideas are extended by optimizing the degree of redundancy used in different parts of the circuit and combining redundant circuit techniques with those of conventional arithmetic. The resultant architecture offers significant improvements in hardware complexity and throughput rate.

A bit-level systolic architecture for implementing a VQ tree search

A bit-level systolic array system for performing a binary tree Vector Quantization codebook search is described. This consists of a linear chain of regular VLSI building blocks and exhibits data rates suitable for a wide range of real-time applications. A technique is described which reduces the computation required at each node in the binary tree to that of a single inner product operation. This method applies to all the common distortion measures (including the Euclidean distance, the Weighted Euclidean distance and the Itakura-Saito distortion measure) and significantly reduces the hardware required to implement the tree search system. © 1990 Kluwer Academic Publishers.

Reconfigurable full-search video motion estimation architecture

In this paper, a new reconfigurable multi-standard architecture is introduced for integer-pixel motion estimation and a standard-cell based chip design study is presented. This has been designed to cover most of the common block-based video compression standards, including MPEG-2, MPEG-4, H.263, H.264, AVS and WMV-9. The architecture exhibits simpler control, high throughput and relative low hardware cost and highly competitive when compared with excising designs for specific video standards. It can also, through the use of control signals, be dynamically reconfigured at run-time to accommodate different system constraint such as the trade-off in power dissipation and video-quality. The computational rates achieved make the circuit suitable for high end video processing applications. Silicon design studies indicate that circuits based on this approach incur only a relatively small penalty in terms of power dissipation and silicon area when compared with implementations for specific standards.

New FFT architecture and chip design for motion compensation based on phase correlation

Details of a new low power FFT processor for use in digital television applications are presented. This has been fabricated using a 0.6 µm CMOS technology and can perform a 64 point complex forward or inverse FFT on real-rime video at up to 18 Megasamples per second. It comprises 0.5 million transistors in a die area of 7.8×8 mm and dissipates 1 W. Its performance, in terms of computational rate per area per watt, is significantly higher than previously reported devices, leading to a cost-effective silicon solution for high quality video processing applications. This is the result of using a novel VLSI architecture which has been derived from a first principles factorisation of the DFT matrix and tailored to a direct silicon implementation.

Promoting a Sense of Place: An International Study of Architecture Centres

This paper details an international research project which examined over 50 architecture centres in 23 countries including four case study subjects:
•Kent Architecture Centre, England
•Chicago Architecture Foundation
•Museum of Finnish Architecture
•Netherlands Architecture Institute
The paper analyzes the project's main findings including issues of definition, reasons for foundation, cultural policy impact and the main goals of architecture centres. It summarizes recommendations for centres as they attempt to reach their aims.

W-Band Planar Wide-Angle Scanning Antenna Architecture

This paper proposes a hybrid scanning antenna architecture for applications in mm-wave intelligent mobile sensing and communications. We experimentally demonstrate suitable W-band leaky-wave antenna prototypes in substrate integrated waveguide (SIW) technology. Three SIW antennas have been designed that within a 6.5 % fractional bandwidth provide beam scanning over three adjacent angular sectors. Prototypes have been fabricated and their performance has been experimentally evaluated. The measured radiation patterns have shown three frequency scanning beams covering angles from 11 to 56 degrees with beamwidth of 10?±?3 degrees within the 88-94 GHz frequency range.

Critical Dialogue in Architecture Studio: Peer Interaction and Feedback

Most tutors in architecture education regard studio-based learning to be rich in feedback due to is dialogic nature. Yet, student perceptions communicated via audits such as the UK National Student Survey appear to contradict this assumption and challenge the efficacy of design studio as a truly discursive learning setting. This paper presents findings from a collaborative study that was undertaken by the Robert Gordon University, Aberdeen, and Queen’s University Belfast that develop a deeper understanding of the role that peer interaction and dialogue plays within feedback processes, and the value that students attribute to these within the overall learning experience.

The paper adopts a broad definition of feedback, with emphasis on formative processes, and including the various kinds of dialogue that typify studio-based learning, and which constitute forms of guidance, direction, and reflection. The study adopted an ethnographic approach, gathering data on student and staff perceptions over the course of an academic year, and utilising methods embracing both quantitative and qualitative data.

The study found that the informal, socially-based peer interaction that characterises the studio is complementary to, and quite distinct from, the learning derived through tutor interaction. The findings also articulate the respective properties of informal and formally derived feedback and the contribution each makes to the quality of studio-based learning. It also identifies limitations in the use or value of peer learning, understanding of which is valuable to enhancing studio learning in architecture.

Understanding Student and Staff Perceptions of Feedback in Architecture: Summary Report

This report presents the results of a collaborative project between Queens University, Belfast and the Robert Gordon University, Aberdeen, and builds on a dialogue initiated during Session 2009-10 through which course guidance and feedback received by students was identified as an area requiring deeper understanding in order to enhance current practice

Defending the Irish Border: The Map of Watchful Architecture

This chapter offers an analysis of a map of the Irish border. The Map of Watchful Architecture charts the history of defensive structures in the border region.

Exploring Virtual-Channel architecture in FPGA based Networks-on-Chip

A novel Networks-on-Chip (NoC) router architecture specified for FPGA based implementation with configurable Virtual-Channel (VC) is presented. Each pipeline stage of the proposed architecture has been optimized so that low packet propagation latency and reduced hardware overhead can be achieved. The proposed architecture enables high performance and cost effective VC NoC based on-chip system interconnects to be deployed on FPGA.

A Generic Reference Software Architecture for Load Balancing over Mirrored Web Servers: NaSr Case Study

With the rapid expansion of the internet and the increasing demand on Web servers, many techniques were developed to overcome the servers' hardware performance limitation. Mirrored Web Servers is one of the techniques used where a number of servers carrying the same "mirrored" set of services are deployed. Client access requests are then distributed over the set of mirrored servers to even up the load. In this paper we present a generic reference software architecture for load balancing over mirrored web servers. The architecture was designed adopting the latest NaSr architectural style [1] and described using the ADLARS [2] architecture description language. With minimal effort, different tailored product architectures can be generated from the reference architecture to serve different network protocols and server operating systems. An example product system is described and a sample Java implementation is presented.