Exploring Virtual-Channel architecture in FPGA based Networks-on-Chip
| Data(s) |
2011
|
|---|---|
| Resumo |
A novel Networks-on-Chip (NoC) router architecture specified for FPGA based implementation with configurable Virtual-Channel (VC) is presented. Each pipeline stage of the proposed architecture has been optimized so that low packet propagation latency and reduced hardware overhead can be achieved. The proposed architecture enables high performance and cost effective VC NoC based on-chip system interconnects to be deployed on FPGA. |
| Identificador | |
| Idioma(s) |
eng |
| Publicador |
Institute of Electrical and Electronics Engineers (IEEE) |
| Direitos |
info:eu-repo/semantics/restrictedAccess |
| Fonte |
Lu , Y , McCanny , J & Sezer , S 2011 , Exploring Virtual-Channel architecture in FPGA based Networks-on-Chip . in 2011 IEEE International SOC Conference (SOCC) . Institute of Electrical and Electronics Engineers (IEEE) , New York , pp. 302-307 , 24th IEEE International System-on-Chip Conference (SOCC) , Taipei , Taiwan, Province of China , 26-28 September . DOI: 10.1109/SOCC.2011.6085089 |
| Tipo |
contributionToPeriodical |
