968 resultados para buffer layers


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In situ ellipsometry and Kerr polarimetry have been used to follow the continuous evolution of the optical and magneto- optical properties of multiple layers of Co and Pd during their growth. Films were sputter deposited onto a Pd buffer layer on glass substrates up to a maximum of N = 10 bi-layer periods according to the scheme glass/Pd(10)Ar x (0.3Co/3Pd) (nm). Magnetic hysteresis measurements taken during the deposition consistently showed strong perpendicular anisotropy at all stages of film growth following the deposition of a single monolayer of Co. Magneto-optic signals associated with the normal-incidence polar Kerr effect indicated strong polarization of Pd atoms at both Co-Pd and Pd-Co interfaces and that the magnitude of the complex magneto-optic Voigt parameter and the magnetic moment of the Pd decrease exponentially with distance from the interface with a decay constant of 1.1 nm(- 1). Theoretical simulations have provided an understanding of the observations and allow the determination of the ultrathin- film values of the elements of the skew-symmetric permittivity tensor that describe the optical and magneto-optical properties for both CO and Pd. Detailed structure in the observed Kerr ellipticity shows distinct Pd-thickness-dependent oscillations with a spatial period of about 1.6 nm that are believed to be associated with quantum well levels in the growing Pd layer.

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A comparison of dc characteristics of fully depleted double-gate (DG) MOSFETs with respect to low-power circuit applications and device scaling has been performed by two-dimensional device simulation. Three different DG MOSFET structures including a conventional N+ polysilicon gate device with highly doped Si layer, an asymmetrical P+/N+ polysilicon gate device with low doped Si layer and a midgap metal gate device with low doped Si layer have been analysed. It was found that DG MOSFET with mid-gap metal, gates yields the best dc parameters for given off-state drain leakage current and highest immunity to the variation of technology parameters (gate length, gate oxide thickness and Si layer thickness). It is also found that an asymmetrical P+/N+ polysilicon gate DG MOSFET design offers comparable dc characteristics, but better parameter immunity to technology tolerances than a conventional DG MOSFET. (C) 2004 Elsevier Ltd. All rights reserved.