Design of silicon IP cores for biorthogonal wavelet transforms

A methodology for rapid silicon design of biorthogonal wavelet transform systems has been developed. This is based on generic, scalable architectures for the forward and inverse wavelet filters. These architectures offer efficient hardware utilisation by combining the linear phase property of biorthogonal filters with decimation and interpolation. The resulting designs have been parameterised in terms of types of wavelet and wordlengths for data and coefficients. Control circuitry is embedded within these cores that allows them to be cascaded for any desired level of decomposition without any interface logic. The time to produce silicon designs for a biorthogonal wavelet system is only the time required to run synthesis and layout tools with no further design effort required. The resulting silicon cores produced are comparable in area and performance to hand-crafted designs. These designs are also portable across a range of foundries and are suitable for FPGA and PLD implementations.

Subpixel interpolation architecture for multistandard video motion estimation

A new reconfigurable subpixel interpolation architecture for multistandard (e.g., MPEG-2, MPEG-4, H.264, and AVS) video motion estimation (ME) is presented. This exploits the mixed use of parallel and serial-input FIR filters to achieve high throughput rate and efficient silicon utilization. Silicon design studies show that this can be implemented using 34.8 × 10 3 gates with area and performance that compares very favorably with specific fixed solutions, e.g., for the H.264 standard alone. This can support SDTV and HDTV applications when implemented in 0.18 µm CMOS technology, with further performance enhancements achievable at 0.13 µm and below. © 2009 IEEE.

Reconfigurable system-on-a-chip motion estimation architecture for multi-standard video coding

A new domain-specific, reconfigurable system-on-a-chip (SoC) architecture is proposed for video motion estimation. This has been designed to cover most of the common block-based video coding standards, including MPEG-2, MPEG-4, H.264, WMV-9 and AVS. The architecture exhibits simple control, high throughput and relatively low hardware cost when compared with existing circuits. It can also easily handle flexible search ranges without any increase in silicon area and can be configured prior to the start of the motion estimation process for a specific standard. The computational rates achieved make the circuit suitable for high-end video processing applications, such as HDTV. Silicon design studies indicate that circuits based on this approach incur only a relatively small penalty in terms of power dissipation and silicon area when compared with implementations for specific standards. Indeed, the cost/performance achieved exceeds that of existing but specific solutions and greatly exceeds that of general purpose field programmable gate array (FPGA) designs.

Sensing Spaces:A Body-oriented Architectural Design Education

The contemporary dominance of visuality has turned our understanding of space into a mode of unidirectional experience that externalizes other sensual capacities of the body while perceiving the built environment. This affects not only architectural practice but also architectural education when an introduction to the concept of space is often challenging, especially for the students who have limited spatial and sensual training. Considering that an architectural work is not perceived as a series of retinal pictures but as a repeated multi-sensory experience, the problem definitions in the design studio need to be disengaged from the dominance of a ‘focused vision’ and be re-constructed in a holistic manner. A method to address this approach is to enable the students to refer to their own sensual experiences of the built environment as a part of their design processes. This paper focuses on a particular approach to the second year architectural design teaching which has been followed in the Department of Architecture at Izmir University of Economics for the last three years. The very first architectural project of the studio and the program, entitled ‘Sensing Spaces’, is conducted as a multi-staged design process including ‘sense games, analyses of organs and their interpretations into space’. The objectives of this four-week project are to explore the sense of space through the design of a three-dimensional assembly, to create an awareness of the significance of the senses in the design process and to experiment with re-interpreted forms of bodily parts. Hence, the students are encouraged to explore architectural space through their ‘tactile, olfactory, auditory, gustative and visual stimuli’. In this paper, based on a series of examples, architectural space is examined beyond its boundaries of structure, form and function, and spatial design is considered as an activity of re-constructing the built environment through the awareness of bodily senses.

A 64-point fourier transform chip for video motion compensation using phase correlation

Details of a new low power fast Fourier transform (FFT) processor for use in digital television applications are presented. This has been fabricated using a 0.6-µm CMOS technology and can perform a 64 point complex forward or inverse FFT on real-time video at up to 18 Megasamples per second. It comprises 0.5 million transistors in a die area of 7.8 × 8 mm and dissipates 1 W. The chip design is based on a novel VLSI architecture which has been derived from a first principles factorization of the discrete Fourier transform (DFT) matrix and tailored to a direct silicon implementation.

Reconfigurable full-search video motion estimation architecture

In this paper, a new reconfigurable multi-standard architecture is introduced for integer-pixel motion estimation and a standard-cell based chip design study is presented. This has been designed to cover most of the common block-based video compression standards, including MPEG-2, MPEG-4, H.263, H.264, AVS and WMV-9. The architecture exhibits simpler control, high throughput and relative low hardware cost and highly competitive when compared with excising designs for specific video standards. It can also, through the use of control signals, be dynamically reconfigured at run-time to accommodate different system constraint such as the trade-off in power dissipation and video-quality. The computational rates achieved make the circuit suitable for high end video processing applications. Silicon design studies indicate that circuits based on this approach incur only a relatively small penalty in terms of power dissipation and silicon area when compared with implementations for specific standards.

New FFT architecture and chip design for motion compensation based on phase correlation

Details of a new low power FFT processor for use in digital television applications are presented. This has been fabricated using a 0.6 µm CMOS technology and can perform a 64 point complex forward or inverse FFT on real-rime video at up to 18 Megasamples per second. It comprises 0.5 million transistors in a die area of 7.8×8 mm and dissipates 1 W. Its performance, in terms of computational rate per area per watt, is significantly higher than previously reported devices, leading to a cost-effective silicon solution for high quality video processing applications. This is the result of using a novel VLSI architecture which has been derived from a first principles factorisation of the DFT matrix and tailored to a direct silicon implementation.

Design of a wideband conformal array antenna system with beamforming and null steering, for application in a DVB-T based passive radar

The use of radars in detecting low flying, small targets is being explored for several decades now. However radar with counter-stealth abilities namely the passive, multistatic, low frequency radars are in the focus recently. Passive radar that uses Digital Video Broadcast Terrestrial (DVB-T) signals as illuminator of opportunity is a major contender in this area. A DVB-T based passive radar requires the development of an antenna array that performs satisfactorily over the entire DVB-T band. At Fraunhofer FHR, there is currently a need for an array antenna to be designed for operation over the 450-900 MHz range with wideband beamforming and null steering capabilities. This would add to the ability of the passive radar in detecting covert targets and would improve the performance of the system. The array should require no mechanical adjustments to inter-element spacing to correspond to the DVB-T carrier frequency used for any particular measurement. Such an array would have an increased flexibility of operation in different environment or locations.

The design of such an array antenna and the applied techniques for wideband beamforming and null steering are presented in the thesis. The interaction between the inter-element spacing, the grating lobes and the mutual couplings had to be carefully studied and an optimal solution was to be reached at that meets all the specifications of the antenna array for wideband applications. Directional beams, nulls along interference directions, low sidelobe levels, polarization aspects and operation along a wide bandwidth of 450-900 MHz were some of the key considerations.

Multi-standard sub-pixel interpolation architecture for video motion estimation

A new domain-specific reconfigurable sub-pixel interpolation architecture for multi-standard video Motion Estimation (ME) is presented. The mixed use of parallel and serial-input FIR filters achieves high throughput rate and efficient silicon utilisation. Flexibility has been achieved by using a multiplexed reconfigurable data-path controlled by a selection signal. Silicon design studies show that this can be implemented using 34.8K gates with area and performance that compares very favourably with existing fixed solutions based solely on the H.264 standard. ©2008 IEEE.

Logic and Memory Design Based on Unequal Error Protection for Voltage-scalable, Robust and Adaptive DSP Systems

In this paper, we propose a system level design approach considering voltage over-scaling (VOS) that achieves error resiliency using unequal error protection of different computation elements, while incurring minor quality degradation. Depending on user specifications and severity of process variations/channel noise, the degree of VOS in each block of the system is adaptively tuned to ensure minimum system power while providing "just-the-right" amount of quality and robustness. This is achieved, by taking into consideration block level interactions and ensuring that under any change of operating conditions, only the "less-crucial" computations, that contribute less to block/system output quality, are affected. The proposed approach applies unequal error protection to various blocks of a system-logic and memory-and spans multiple layers of design hierarchy-algorithm, architecture and circuit. The design methodology when applied to a multimedia subsystem shows large power benefits ( up to 69% improvement in power consumption) at reasonable image quality while tolerating errors introduced due to VOS, process variations, and channel noise.

Evaluation of Video Presentation to Deliver Surgical Anatomy Teaching

Title Evaluation of Video Presentation to Deliver Surgical Anatomy Teaching

Authors Walsh I.K., Boohan M., Dorman A.

Objectives To evaluate the efficacy of newly introduced video presentation to deliver Surgical Anatomy teaching to undergraduate medical students.

Design and Setting Qualitative and quantitative study using questionnaires and focus groups, employing students undertaking the perioperative medicine module of the phase 4 undergraduate medical curriculum at Queen’s University Belfast.

Outcome Measures To determine:
(1) if video presentation is effective in delivering surgical anatomy teaching,
(2) student’s learning preferences regarding this teaching method.
Results The questionnaire response rate was 89% (216 of 244 students; female: male ratio 1.25) and 42 students participated in 6 focus groups. Mean questionnaire responses indicated a favourable opinion on quality assurance items, with a mixed response to video presentation as a learning method. 71% of students preferred to receive a lecture in person, rather than via video presentation. There were no statistically significant differences between genders regarding learning preferences in general and regarding video versus live presentation in particular. Exploratory factor analysis demonstrated that favourable responses to video presentation were strongly associated with perceived audiovisual quality and learning preferences (Cronbach’s alpha coefficient 0.77), with 72% of students considering video presentation worthwhile. Positive perception of overall quality was strongly associated with learning preferences as well as more generic quality assurance issues (80% students; alpha coefficient 0.83).
The results were supported by triangulation of the above quantitative data with qualitative data generated by the focus groups. Students further articulated the view that video presentation may be more appropriate and effective in a mixed method setting.

Reference Basu Roy R, McMahon GT. Video-based cases disrupt deep critical thinking in problem-based learning. Med Educ 2012 Apr;46(4):426-435.

Designing games for older adults: an affordance based approach

The main purpose of this study is to determine the game principles that need to be adopted in order to create an enjoyable and engaging game experience for older adults, whilst ensuring that the purpose of the game, encouraging upper limb mobility, is respected. The study reported in this paper involved a group of older adults who played and gave feedback on an early game prototype which feed into the design modification process. Each player's action capabilities were measured and taken into account in the design process. This helped ensure that opportunities for action that the game afforded were adapted to players' need.

The Development of TASTER, a Cognitive Training Game Using Human-Centered Design, Tailored for Children with Global and Specific Cognitive Impairments

Children with Prader-Willi syndrome often exhibit challenging behavior in response to changes to routine. This phenomenon has been linked to a deficit in task switching ability which has been observed in children with the syndrome. TASTER is a cognitive training game which is being designed with input from a group of children with Prader- Willi syndrome, which aims to train task switching ability and thus reduce associated challenging behavior.