Spatial Demultiplexing in the sub-millimeter wave band using multlayer free-standing frequency selective surfaces

In this paper, we show that a multilayer freestanding slot array can be designed to give an insertion loss which is significantly lower than the value obtainable from a conventional dielectric backed printed frequency selective surface (FSS). This increase in filter efficiency is highlighted by comparing the performance of two structures designed to provide frequency selective beamsplitting in the quasioptical feed train of a submillimeter wave space borne radiometer. A two layer substrateless FSS providing more than 20 dB of isolation between the bands 316.5â??325.5 GHz and 349.5â??358.5 GHz, gives an insertion loss of 0.6 dB when the filter is orientated at 45 incidence in the TM plane, whereas the loss exhibited by a conventional printed FSS is in excess of 2 dB. A similar frequency response can be obtained in the TE plane, but here a triple screen structure is required and the conductor loss is shown to be comparable to the absorption loss of a dielectric backed FSS. Experimental devices have been fabricated using a precision micromachining technique. Transmission measurements performed in the range 250â??360 GHz are in good agreement with the simulated spectral performance of the individual periodic screens and the two multilayer freestanding FSS structures.

Micromachined 300GHz high Q resonant slot frequency selective surface filter

The design of a low loss quasi-optical beam splitter which is required to provide efficient diplexing of the bands 316.5-325.5 GHz and 349.5-358.5 GHz is presented. To minimise the filter insertion loss, the chosen architecture is a three-layer freestanding array of dipole slot elements. Floquet modal analysis and finite element method computer models are used to establish the geometry of the periodic structure and to predict its spectral response. Two different micromachining approaches have been employed to fabricate close packed arrays of 460 mm long elements in the screens that form the basic building block of the 30mm diameter multilayer frequency selective surface. Comparisons between simulated and measured transmission coefficients for the individual dichroic surfaces are used to determine the accuracy of the computer models and to confirm the suitability of the fabrication methods.

LPCVD of tungsten by selective deposition on silicon

Beta-phase W, selectively grown at 440C had resistivity 20 micro-ohm cm and maximum layer thickness 100nm. Hydrogen passivation proved essential in this process. Higher deposition temperatures resulted in increased layer thickness but incorporated WSi2 and alpha- phase W. Self limiting W grown on polycrystalline and heavily doped silicon yielded reduced thickness. Boron is involved in the WF6 reduction reaction but phosphorus is not and becomes incorporated in the W layer. The paper establishes an optimised and novel CVD process suited to IC contact technology. A funded technology transfer contract with National Semiconductor Greenock (M Fallon) resulted from this work.

Tungsten Silicide Contacts to Polycrystalline Silicon and Silicon-Germanium Alloys

Novel CVD WSi2 technology with low series and contact resistance in SiGe HBTs was achieved. Specific contact resistance to Si1-xGex with 0

Electrical Characterisation of SOI Substrates Incorporating WSix Ground Planes

Silicon-on-insulator (SOI) substrates incorporating tungsten silicide ground planes (GPs) have been shown to offer the lowest reported crosstalk figure of merit for application in mixed signal integrated circuits. The inclusion of the silicide layer in the structure may lead to stress or defects in the overlying SOI layers and resultant degradation of device performance. It is therefore essential to establish the quality of the silicon on the GPSOI substrate. MOS capacitor structures have been employed in this paper to characterize these GPSOI substrates for the first time. High quality MOS capacitor characteristics have been achieved with minority carrier lifetime of similar to 0.8 ms. These results show that the substrate is suitable for device manufacture with no degradation in the silicon due to stress or metallic contamination resulting from the inclusion of the underlying silicide layer.

Ultralow Silicon Substrate Noise Crosstalk Using Metal Faraday Cages in an SOI Technology

In mixed signal integrated circuits noise from the digital circuitry can upset the sensitive analogue circuitry. The Faraday cage structure reported here is based on the unique ground plane SOI technology developed some of the authors. The suppression of crosstalk achieved is an order of magnitude greater than that previously published for frequencies up to 10 GHz. The significance of the technology will be even greater as the operating frequency is increased. This collaborative EPSRC project was judge as tending to outstanding.

SiGe HBTs on Bonded SOI Incorporating Buried Silicide Layers

The performance of silicon bipolar transistors has been significantly improved by the use of ultra narrow base layers of SiGe. To further improve device performance by minimising parasitic resistance and capacitance the authors produced an unique silicon-on-insulator (SOI) substrate incorporating a buried tungsten disilicide layer. This structure forms the basis of a recent submission by Zarlink Semiconductors ( Silvaco, DeMontfort & Queen�s) to DTI for high voltage devices for automotive applications. The Queen�s part of the original EPSRC project was rated as tending to outstanding.

Effect of Rapid Thermal Annealing on the Structure and Magnetic Properties of Chemical Vapour Deposition Cobalt Layers

Future read heads in hard disc storage require high conformal coatings of metal magnetic layers over high aspect ratio profiles. This paper describes pioneering work on the use of MOCVD for the deposition of cobalt layers. While pure cobalt layers could be deposited at 400C their magnetic properties are poor. It was found that the magnetic properties of the layers could be significantly enhanced with an optimised rapid thermal anneal. This work was sponsored by Seagate Technology and led to a follow up PhD studentship on the co-deposition of cobalt and iron by MOCVD.

Thin film sputtered silicon for silicon wafer bonding applications

The transfer of functional integrated circuit layers to other substrates is being investigated for smart-sensors, MEMS, 3-D ICs and mixed semiconductor circuits. There is a need for a planarisation and bondable layer which can be deposited at low temperature and which is IC compatible. This paper describes for the first time the successful use of sputtered silicon in this role for applications as outlined above where high temperature post bond anneals are not required. It also highlights the problems of using sputtered silicon as a bonding layer in applications where post bond temperatures greater than 400C are required.