Cryogenic Operation of Junctionless Nanowire Transistors

This letter presents the properties of nMOS junctionless nanowire transistors (JNTs) under cryogenic operation. Experimental results of drain current, subthreshold slope, maximum transconductance at low electric field, and threshold voltage, as well as its variation with temperature, are presented. Unlike in classical devices, the drain current of JNTs decreases when temperature is lowered, although the maximum transconductance increases when the temperature is lowered down to 125 K. An analytical model for the threshold voltage is proposed to explain the influence of nanowire width and doping concentration on its variation with temperature. It is shown that the wider the nanowire or the lower the doping concentration, the higher the threshold voltage variation with temperature.

Universal zero-bias conductance for the single-electron transistor

The thermal dependence of the zero-bias conductance for the single electron transistor is the target of two independent renormalization-group approaches, both based on the spin-degenerate Anderson impurity model. The first approach, an analytical derivation, maps the Kondo-regime conductance onto the universal conductance function for the particle-hole symmetric model. Linear, the mapping is parametrized by the Kondo temperature and the charge in the Kondo cloud. The second approach, a numerical renormalization-group computation of the conductance as a function the temperature and applied gate voltages offers a comprehensive view of zero-bias charge transport through the device. The first approach is exact in the Kondo regime; the second, essentially exact throughout the parametric space of the model. For illustrative purposes, conductance curves resulting from the two approaches are compared.

Symmetry controlled spin polarized conductance in Au nanowires

The fact that the resistance of propagating electrons in solids depends on their spin orientation has led to a new field called spintronics. With the parallel advances in nanoscience, it is now possible to talk about nanospintronics. Many works have focused on the study of charge transport along nanosystems, such as carbon nanotubes, graphene nanoribbons, or metallic nanowires, and spin dependent transport properties at this scale may lead to new behaviors due to the manipulation of a small number of spins. Metal nanowires have been studied as electric contacts where atomic and molecular insertions can be constructed. Here we describe what might be considered the ultimate spin device, namely, a Au thin nanowire with one Co atom bridging its two sides. We show that this system has strong spin dependent transport properties and that its local symmetry can dramatically change them, leading to a significant spin polarized conductance.

Low subthreshold slope in junctionless multigate transistors

The improvement of subthreshold slope due to impact ionization is compared between ""standard"" inversion-mode multigate silicon nanowire transistors and junctionless transistors. The length of the region over which impact ionization takes place, as well as the amplitude of the impact ionization rate are found to be larger in the junctionless devices, which reduces the drain voltage necessary to obtain a sharp subthreshold slope. (C) 2010 American Institute of Physics. [doi: 10.1063/1.3358131]

Universal zero-bias conductance through a quantum wire side-coupled to a quantum dot

A numerical renormalization-group study of the conductance through a quantum wire containing noninteracting electrons side-coupled to a quantum dot is reported. The temperature and the dot-energy dependence of the conductance are examined in the light of a recently derived linear mapping between the temperature-dependent conductance and the universal function describing the conductance for the symmetric Anderson model of a quantum wire with an embedded quantum dot. Two conduction paths, one traversing the wire, the other a bypass through the quantum dot, are identified. A gate potential applied to the quantum wire is shown to control the current through the bypass. When the potential favors transport through the wire, the conductance in the Kondo regime rises from nearly zero at low temperatures to nearly ballistic at high temperatures. When it favors the dot, the pattern is reversed: the conductance decays from nearly ballistic to nearly zero. When comparable currents flow through the two channels, the conductance is nearly temperature independent in the Kondo regime, and Fano antiresonances in the fixed-temperature plots of the conductance as a function of the dot-energy signal interference between them. Throughout the Kondo regime and, at low temperatures, even in the mixed-valence regime, the numerical data are in excellent agreement with the universal mapping.

Harmonic Distortion of Unstrained and Strained FinFETs Operating in Saturation

The harmonic distortion (HD) exhibited by un-strained and biaxially strained fin-shaped field-effect transistors operating in saturation as single-transistor amplifiers has been investigated for devices with different channel lengths L and fin widths W(fin). The study has been performed through device characterization, 3-D device simulations, and modeling. Nonlinearity has been evaluated in terms of second- and third-order HDs (HD2 and HD3, respectively), and a discussion on its physical sources has been carried out. Also, the influence of the open-loop voltage gain AV in HD has been observed.

Trapezoidal SOI FinFET analog parameters` dependence on cross-section shape

The trapezium is often a better approximation for the FinFET cross-section shape, rather than the design-intended rectangle. The frequent width variations along the vertical direction, caused by the etching process that is used for fin definition, may imply in inclined sidewalls and the inclination angles can vary in a significant range. These geometric variations may cause some important changes in the device electrical characteristics. This work analyzes the influence of the FinFET sidewall inclination angle on some relevant parameters for analog design, such as threshold voltage, output conductance, transconductance, intrinsic voltage gain (A V), gate capacitance and unit-gain frequency, through 3D numeric simulation. The intrinsic gain is affected by alterations in transconductance and output conductance. The results show that both parameters depend on the shape, but in different ways. Transconductance depends mainly on the sidewall inclination angle and the fixed average fin width, whereas the output conductance depends mainly on the average fin width and is weakly dependent on the sidewall inclination angle. The simulation results also show that higher voltage gains are obtained for smaller average fin widths with inclination angles that correspond to inverted trapeziums, i.e. for shapes where the channel width is larger at the top than at the transistor base because of the higher attained transconductance. When the channel top is thinner than the base, the transconductance degradation affects the intrinsic voltage gain. The total gate capacitances also present behavior dependent on the sidewall angle, with higher values for inverted trapezium shapes and, as a consequence, lower unit-gain frequencies.

Threshold voltages of SOI MuGFETs

The multiple-gate field-effect transistor (MuGFET) is a device with a gate folded on different sides of the channel region. They are one of the most promising technological solutions to create high-performance ultra-scaled SOI CMOS. In this work, the behavior of the threshold voltage in double-gate, triple-gate and quadruple-gate SOI transistors with different channel doping concentrations is studied through three-dimensional numerical simulation. The results indicated that for double-gate transistors, one or two threshold voltages can be observed, depending on the channel doping concentration. However, in triple-gate and quadruple-gate it is possible to observe up to four threshold voltages due to the corner effect and the different doping concentration between the top and bottom of the Fin. (C) 2008 Elsevier Ltd. All rights reserved.

Junctionless Multiple-Gate Transistors for Analog Applications

This paper presents the evaluation of the analog properties of nMOS junctionless (JL) multigate transistors, comparing their performance with those exhibited by inversion-mode (IM) trigate devices of similar dimensions. The study has been performed for devices operating in saturation as single-transistor amplifiers, and we have considered the dependence of the analog properties on fin width W(fin) and temperature T. Furthermore, this paper aims at providing a physical insight into the analog parameters of JL transistors. For that, in addition to device characterization, 3-D device simulations were performed. It is shown that, depending on gate voltage, JL devices can present both larger Early voltage V(EA) and larger intrinsic voltage gain A(V) than IM devices of similar dimensions. In addition, V(EA) and A(V) are always improved in JL devices when the temperature is increased, whereas they present a maximum value around room temperature for IM transistors.

Advantages of graded-channel SOI nMOSFETs for application as source-follower analog buffer

In this work the performance of graded-channel (CC) SOI MOSFETs operating as source-follower buffers is presented. The experimental analysis is performed by comparing the gain and linearity of buffers implemented with CC and standard SOI MOS devices considering the same mask dimensions. It is shown that by using CC devices, buffer gain very close to the theoretical limit can be achieved, with improved linearity, while for standard devices the gain departs from the theoretical value depending on the inversion level imposed by the bias current and input voltage. Two-dimensional numerical simulations were performed in order to confirm some hypotheses proposed to explain the gain behavior observed in the experimental data. By using numerical simulations the channel length has been varied, showing that the gain of buffers implemented with CC devices remains close to the theoretical limit even when short-channel devices are adopted. It has also been shown that the length of a source-follower buffer using CC devices can be reduced by a factor of 5, in comparison with a standard Sol MOSFET, without gain loss or linearity degradation. (C) 2008 Elsevier Ltd. All rights reserved.

Harmonic distortion analysis of double gate graded-channel MOSFETs operating in saturation

In this work we present an analysis of harmonic distortion (HD) in graded-channel (GC) gate-all-a round (GAA) devices operating in saturation region for analog applications. The study has been performed through device characterization and two-dimensional process and device simulations. The overall study has been done on the total and third order HDs. When applied in the saturation regime as an amplifier, the GC outperforms conventional GAA transistors presenting simultaneously higher transconductance, lower drain output conductance and more than 15 dB improved linearity. The influence of channel length reduction on the H D is also analyzed. Although slight linearity degradation is observed in both the conventional and the GC devices when reducing the channel length, the HD presented by the GC transistor is significantly lower than the one showed by conventional device for any Studied channel length. This allows AC input signal amplitude up to 20 times higher than the conventional GAA for a same specified distortion level. (C) 2008 Elsevier Ltd. All rights reserved.

The role of citrate precursors on the morphology of lanthanide oxides obtained by thermal decomposition

Two series of lanthanide oxides with different morphologies were synthesized through calcinations of two types of citrate polymeric precursors. These oxides were characterized by XRD patterns, SEM electronic microscopy, and N(2) adsorption isotherms. SEM microscopy analysis showed that the calcination of crystalline fibrous precursors [Ln(2)(LH)(3)center dot 2H(2)O] (L = citrate) originated fibrous shaped particles. On the other hand, the calcination of irregular shaped particles of precursors [LnL center dot xH(2)O] originated irregular shaped particles of oxide, pointing out a morphological template effect of precursors on the formation of the respective oxides.

Reversible and irreversible magnetization components behavior in Ni nanowires

Polycrystalline Ni nanowires were electrodeposited in nanoporous anodized alumina membranes with mean diameter of approximately 42 nm. Their magnetic properties were studied at 300 K, by measurements of recoil curves from demagnetized state and also from saturated state. M(rev) and M(irr) components were obtained and M(rev)(M(irr)) H curves were constructed from the experimental data. These curves showed a behavior that suggests a non-uniform reversal mode influenced by the presence of dipolar interactions in the system. A qualitative approach to this behavior is obtained using a Stoner-Wohlfarth model modified by a mean field term and local interaction fields. (C) 2008 Elsevier B.V. All rights reserved.

Characterizing magnetic interactions in Ni nanowires by FORC analysis

Polycrystalline Ni nanowires with different diameters were electrodeposited in nanoporous anodized alumina membranes. First-Order Reversal Curves (FORCs) were measured and FORC distributions were calculated. They clearly showed an asymmetric behavior with a strong maximum at negative interaction fields, evidencing the dominant demagnetizing interactions which depend on the geometry of the nanowires. (C) 2008 Elsevier B.V. All rights reserved.

Effects of Side-Chain and Electron Exchange Correlation on the Band Structure of Perylene Diimide Liquid Crystals: A Density Functional Study

The structural and electronic properties of perylene diimide liquid crystal PPEEB are studied using ab initio methods based on the density functional theory (I)FT). Using available experimental crystallographic data as a guide, we propose a detailed structural model for the packing of solid PPEEB. We find that due to the localized nature of the band edge wave function, theoretical approaches beyond the standard method, such as hybrid functional (PBE0), are required to correctly characterize the band structure of this material. Moreover, unlike previous assumptions, we observe the formation of hydrogen bonds between the side chains of different molecules, which leads to a dispersion of the energy levels. This result indicates that the side chains of the molecular crystal not only are responsible for its structural conformation but also can be used for tuning the electronic and optical properties of these materials.