Cryogenic Operation of Junctionless Nanowire Transistors

This letter presents the properties of nMOS junctionless nanowire transistors (JNTs) under cryogenic operation. Experimental results of drain current, subthreshold slope, maximum transconductance at low electric field, and threshold voltage, as well as its variation with temperature, are presented. Unlike in classical devices, the drain current of JNTs decreases when temperature is lowered, although the maximum transconductance increases when the temperature is lowered down to 125 K. An analytical model for the threshold voltage is proposed to explain the influence of nanowire width and doping concentration on its variation with temperature. It is shown that the wider the nanowire or the lower the doping concentration, the higher the threshold voltage variation with temperature.

Junctionless Multiple-Gate Transistors for Analog Applications

This paper presents the evaluation of the analog properties of nMOS junctionless (JL) multigate transistors, comparing their performance with those exhibited by inversion-mode (IM) trigate devices of similar dimensions. The study has been performed for devices operating in saturation as single-transistor amplifiers, and we have considered the dependence of the analog properties on fin width W(fin) and temperature T. Furthermore, this paper aims at providing a physical insight into the analog parameters of JL transistors. For that, in addition to device characterization, 3-D device simulations were performed. It is shown that, depending on gate voltage, JL devices can present both larger Early voltage V(EA) and larger intrinsic voltage gain A(V) than IM devices of similar dimensions. In addition, V(EA) and A(V) are always improved in JL devices when the temperature is increased, whereas they present a maximum value around room temperature for IM transistors.

Low subthreshold slope in junctionless multigate transistors

The improvement of subthreshold slope due to impact ionization is compared between ""standard"" inversion-mode multigate silicon nanowire transistors and junctionless transistors. The length of the region over which impact ionization takes place, as well as the amplitude of the impact ionization rate are found to be larger in the junctionless devices, which reduces the drain voltage necessary to obtain a sharp subthreshold slope. (C) 2010 American Institute of Physics. [doi: 10.1063/1.3358131]

Universal zero-bias conductance for the single-electron transistor

The thermal dependence of the zero-bias conductance for the single electron transistor is the target of two independent renormalization-group approaches, both based on the spin-degenerate Anderson impurity model. The first approach, an analytical derivation, maps the Kondo-regime conductance onto the universal conductance function for the particle-hole symmetric model. Linear, the mapping is parametrized by the Kondo temperature and the charge in the Kondo cloud. The second approach, a numerical renormalization-group computation of the conductance as a function the temperature and applied gate voltages offers a comprehensive view of zero-bias charge transport through the device. The first approach is exact in the Kondo regime; the second, essentially exact throughout the parametric space of the model. For illustrative purposes, conductance curves resulting from the two approaches are compared.

Symmetry controlled spin polarized conductance in Au nanowires

The fact that the resistance of propagating electrons in solids depends on their spin orientation has led to a new field called spintronics. With the parallel advances in nanoscience, it is now possible to talk about nanospintronics. Many works have focused on the study of charge transport along nanosystems, such as carbon nanotubes, graphene nanoribbons, or metallic nanowires, and spin dependent transport properties at this scale may lead to new behaviors due to the manipulation of a small number of spins. Metal nanowires have been studied as electric contacts where atomic and molecular insertions can be constructed. Here we describe what might be considered the ultimate spin device, namely, a Au thin nanowire with one Co atom bridging its two sides. We show that this system has strong spin dependent transport properties and that its local symmetry can dramatically change them, leading to a significant spin polarized conductance.

Sequential IRMPD of XGe(OEt)(4)(-) ions: Gas-phase synthesis of novel oxy-germanium anions

The gas-phase ion/molecule reactions of F(-) and EtO(-) with Ge(OEt)(4) yield readily and exclusively pentacoordinated complexes XGe(OEt)(4)(-) (X = F, EtO) at pressures in the 10(-8) T range as observed by FT-ICR techniques. These hypervalent species are prone to undergo sequential fragmentations induced by infrared multiphoton excitation that lead to a variety of germyl and germanate anions. In the case of FGe(OEt)(4)(-), three primary competitive channels are observed in the IRMPD process that can be identified as (EtO)(3)GeO(-), F(EtO)(2)GeO(-) and (EtO)(3)Ge(-). Ab initio calculations have been carried out to characterize the primary fragmentation paths induced by IRMPD and the most favorable structure of the resulting anions. The gas-phase acidity of a number of these germanium-containing ions have been estimated by bracketing experiments and by theoretical calculations. Germanate anions such as (EtO)(3)GeO(-) undergo some interesting reactions with H(2)S to give rise to anions such as (EtO)(3)GeS(-) and (EtO)(2)Ge(OH)S(-). (C) 2010 Elsevier B.V. All rights reserved.

Phase transformation and residual stress probed by Raman spectroscopy in diamond-turned single crystal silicon

Single-point diamond turning of monocrystalline semiconductors is an important field of research within brittle materials machining. Monocrystalline silicon samples with a (100) orientation have been diamond turned under different cutting conditions (feed rate and depth of cut). Micro-Raman spectroscopy and atomic force microscopy have been used to assess structural alterations and surface finish of the samples diamond turned under ductile and brittle modes. It was found that silicon undergoes a phase transformation when machined in the ductile mode. This phase transformation is evidenced by the creation of an amorphous surface layer after machining which has been probed by Raman scattering. Compressive residual stresses are estimated for the machined surface and it is observed that they decrease with an increase in the feed rate and depth of cut. This behaviour has been attributed to the formation of subsurface cracks when the feed rate is higher than or equal to 2.5 mu m/rev. The surface roughness was observed to vary with the feed rate and the depth of cut. An increase in the surface roughness was influenced by microcrack formation when the feed rate reached 5.0 mu m/rev. Furthermore, a high-pressure phase transformation induced by the tool/material interaction and responsible for the ductile response of this typical brittle material is discussed based upon the presented Raman spectra. The application of this machining technology finds use for a wide range of high quality components, for example the creation of a micrometre-range channel for microfluidic devices as well as microlenses used in the infrared spectrum range.

Near-infrared third-order nonlinearity of PbO-GeO(2) films containing Cu and Cu(2)O nanoparticles

We report measurements of the nonlinear (NL) refractive index n(2) of lead-germanium films (LGFs) containing Cu and Cu(2)O nanoparticles (NPs). The thermally managed eclipse Z-scan technique with 150 fs pulses from a laser operating at 800 nm was used. The NL refractive index measured, n(2)=6.3x10(-12) cm(2)/W has electronic origin and the NL absorption coefficient alpha(2) is smaller than 660 cm/GW. The figure of merit n(2)/lambda alpha(2) is enhanced by more than two orders of magnitude in comparison with the result for the LGFs without the copper based NPs. (C) 2008 American Institute of Physics.

Universal zero-bias conductance through a quantum wire side-coupled to a quantum dot

A numerical renormalization-group study of the conductance through a quantum wire containing noninteracting electrons side-coupled to a quantum dot is reported. The temperature and the dot-energy dependence of the conductance are examined in the light of a recently derived linear mapping between the temperature-dependent conductance and the universal function describing the conductance for the symmetric Anderson model of a quantum wire with an embedded quantum dot. Two conduction paths, one traversing the wire, the other a bypass through the quantum dot, are identified. A gate potential applied to the quantum wire is shown to control the current through the bypass. When the potential favors transport through the wire, the conductance in the Kondo regime rises from nearly zero at low temperatures to nearly ballistic at high temperatures. When it favors the dot, the pattern is reversed: the conductance decays from nearly ballistic to nearly zero. When comparable currents flow through the two channels, the conductance is nearly temperature independent in the Kondo regime, and Fano antiresonances in the fixed-temperature plots of the conductance as a function of the dot-energy signal interference between them. Throughout the Kondo regime and, at low temperatures, even in the mixed-valence regime, the numerical data are in excellent agreement with the universal mapping.

Atomistic origins of the phase transition mechanism in Ge(2)Sb(2)Te(5)

The fast and reversible phase transition mechanism between crystalline and amorphous phases of Ge(2)Sb(2)Te(5) has been in debate for several years. Through employing first-principles density functional theory calculations, we identify a direct structural link between the metastable crystalline and amorphous phases. The phase transition is driven by the displacement of Ge atoms along the rocksalt [111] direction from stable octahedron to high energy unstable tetrahedron sites close to the intrinsic vacancy regions, which generates a high energy intermediate phase between metastable and amorphous phases. Due to the instability of Ge at the tetrahedron sites, the Ge atoms naturally shift away from those sites, giving rise to the formation of local-ordered fourfold motifs and the long-range structural disorder. Intrinsic vacancies, which originate from Sb(2)Te(3), lower the energy barrier for Ge displacements, and hence, their distribution plays an important role in the phase transition. The high energy intermediate configuration can be obtained experimentally by applying an intense laser beam, which overcomes the thermodynamic barrier from the octahedron to tetrahedron sites. The high figure of merit of Ge(2)Sb(2)Te(5) is achieved from the optimal combination of intrinsic vacancies provided by Sb(2)Te(3) and the instability of the tetrahedron sites provided by GeTe.

Estimation of the thickness and the optical parameters of several stacked thin films using optimization

The reverse engineering problem addressed in the present research consists of estimating the thicknesses and the optical constants of two thin films deposited on a transparent substrate using only transmittance data through the whole stack. No functional dispersion relation assumptions are made on the complex refractive index. Instead, minimal physical constraints are employed, as in previous works of some of the authors where only one film was considered in the retrieval algorithm. To our knowledge this is the first report on the retrieval of the optical constants and the thickness of multiple film structures using only transmittance data that does not make use of dispersion relations. The same methodology may be used if the available data correspond to normal reflectance. The software used in this work is freely available through the PUMA Project web page (http://www.ime.usp.br/similar to egbirgin/puma/). (C) 2008 Optical Society of America

Harmonic Distortion of Unstrained and Strained FinFETs Operating in Saturation

The harmonic distortion (HD) exhibited by un-strained and biaxially strained fin-shaped field-effect transistors operating in saturation as single-transistor amplifiers has been investigated for devices with different channel lengths L and fin widths W(fin). The study has been performed through device characterization, 3-D device simulations, and modeling. Nonlinearity has been evaluated in terms of second- and third-order HDs (HD2 and HD3, respectively), and a discussion on its physical sources has been carried out. Also, the influence of the open-loop voltage gain AV in HD has been observed.

Trapezoidal SOI FinFET analog parameters` dependence on cross-section shape

The trapezium is often a better approximation for the FinFET cross-section shape, rather than the design-intended rectangle. The frequent width variations along the vertical direction, caused by the etching process that is used for fin definition, may imply in inclined sidewalls and the inclination angles can vary in a significant range. These geometric variations may cause some important changes in the device electrical characteristics. This work analyzes the influence of the FinFET sidewall inclination angle on some relevant parameters for analog design, such as threshold voltage, output conductance, transconductance, intrinsic voltage gain (A V), gate capacitance and unit-gain frequency, through 3D numeric simulation. The intrinsic gain is affected by alterations in transconductance and output conductance. The results show that both parameters depend on the shape, but in different ways. Transconductance depends mainly on the sidewall inclination angle and the fixed average fin width, whereas the output conductance depends mainly on the average fin width and is weakly dependent on the sidewall inclination angle. The simulation results also show that higher voltage gains are obtained for smaller average fin widths with inclination angles that correspond to inverted trapeziums, i.e. for shapes where the channel width is larger at the top than at the transistor base because of the higher attained transconductance. When the channel top is thinner than the base, the transconductance degradation affects the intrinsic voltage gain. The total gate capacitances also present behavior dependent on the sidewall angle, with higher values for inverted trapezium shapes and, as a consequence, lower unit-gain frequencies.

Threshold voltages of SOI MuGFETs

The multiple-gate field-effect transistor (MuGFET) is a device with a gate folded on different sides of the channel region. They are one of the most promising technological solutions to create high-performance ultra-scaled SOI CMOS. In this work, the behavior of the threshold voltage in double-gate, triple-gate and quadruple-gate SOI transistors with different channel doping concentrations is studied through three-dimensional numerical simulation. The results indicated that for double-gate transistors, one or two threshold voltages can be observed, depending on the channel doping concentration. However, in triple-gate and quadruple-gate it is possible to observe up to four threshold voltages due to the corner effect and the different doping concentration between the top and bottom of the Fin. (C) 2008 Elsevier Ltd. All rights reserved.

Advantages of graded-channel SOI nMOSFETs for application as source-follower analog buffer

In this work the performance of graded-channel (CC) SOI MOSFETs operating as source-follower buffers is presented. The experimental analysis is performed by comparing the gain and linearity of buffers implemented with CC and standard SOI MOS devices considering the same mask dimensions. It is shown that by using CC devices, buffer gain very close to the theoretical limit can be achieved, with improved linearity, while for standard devices the gain departs from the theoretical value depending on the inversion level imposed by the bias current and input voltage. Two-dimensional numerical simulations were performed in order to confirm some hypotheses proposed to explain the gain behavior observed in the experimental data. By using numerical simulations the channel length has been varied, showing that the gain of buffers implemented with CC devices remains close to the theoretical limit even when short-channel devices are adopted. It has also been shown that the length of a source-follower buffer using CC devices can be reduced by a factor of 5, in comparison with a standard Sol MOSFET, without gain loss or linearity degradation. (C) 2008 Elsevier Ltd. All rights reserved.