Material effects on stress-induced defect generation in trenched silicon-on-insulator structures

We have investigated the influence of the material properties of the silicon device layer on the generation of defects, and in particular slip dislocations, in trenched and refilled fusion-bonded silicon-on-insulator structures. A strong dependence of the ease of slip generation on the type of dopant species was observed, with the samples falling into three basic categories; heavily boron-doped silicon showed ready slip generation, arsenic and antimony-doped material was fairly resistant to slip, while silicon moderately or lightly doped with phosphorous or boron gave intermediate behavior. The observed behavior appears to be controlled by differences in the dislocation generation mechanism rather than by dislocation mobility. The introduction of an implanted buried layer at the bonding interface was found to result in an increase in slip generation in the silicon, again with a variation according to the dopant species. Here, the greatest slip occurred for both boron and antimony-implanted samples. The weakening of the implanted material may be related to the presence of a band of precipitates observed in the silicon near the bonding interface. (C) 2001 The Electrochemical Society.

SiGe HBTs on Bonded SOI Incorporating Buried Silicide Layers

The performance of silicon bipolar transistors has been significantly improved by the use of ultra narrow base layers of SiGe. To further improve device performance by minimising parasitic resistance and capacitance the authors produced an unique silicon-on-insulator (SOI) substrate incorporating a buried tungsten disilicide layer. This structure forms the basis of a recent submission by Zarlink Semiconductors ( Silvaco, DeMontfort & Queen�s) to DTI for high voltage devices for automotive applications. The Queen�s part of the original EPSRC project was rated as tending to outstanding.

Electrical Characterisation of SOI Substrates Incorporating WSix Ground Planes

Silicon-on-insulator (SOI) substrates incorporating tungsten silicide ground planes (GPs) have been shown to offer the lowest reported crosstalk figure of merit for application in mixed signal integrated circuits. The inclusion of the silicide layer in the structure may lead to stress or defects in the overlying SOI layers and resultant degradation of device performance. It is therefore essential to establish the quality of the silicon on the GPSOI substrate. MOS capacitor structures have been employed in this paper to characterize these GPSOI substrates for the first time. High quality MOS capacitor characteristics have been achieved with minority carrier lifetime of similar to 0.8 ms. These results show that the substrate is suitable for device manufacture with no degradation in the silicon due to stress or metallic contamination resulting from the inclusion of the underlying silicide layer.

Investigation of precision grinding process for production of silicon diaphragms

The application of precision grinding for the formation of a silicon diaphragm is investigated. The test structures involved 2-6 mm diam diaphragms with thicknesses in the range of 25-150 //m. When grinding is performed without supporting the diaphragm, bending occurs due to nonuniform removal of the silicon material over the diaphragm region. The magnitude of bending depends on the µNal thickness of the diaphragm. The results demonstrate that the use of a porous silicon support can significantly reduce the amount of bending, by a factor of up to 300 in the case of 50 m thick diaphragms. The use of silicon on insulator (SOI) technology can also suppress or eliminate bending although this may be a less economical process. Stress measurements in the diaphragms were performed using x-ray and Raman spectroscopies. The results show stress of the order of 1 X107-! X108 Pa in unsupported and supported by porous silicon diaphragms while SOI technology provides stress-free diaphragms. Results obtained from finite element method analysis to determine deterioration in the performance of a 6 mm diaphragm due to bending are presented. These results show a 10% reduction in performance for a 75 µm thick diaphragm with bending amplitude of 30 fim, but negligible reduction if the bending is reduced to