Electrical Characterisation of SOI Substrates Incorporating WSix Ground Planes

Silicon-on-insulator (SOI) substrates incorporating tungsten silicide ground planes (GPs) have been shown to offer the lowest reported crosstalk figure of merit for application in mixed signal integrated circuits. The inclusion of the silicide layer in the structure may lead to stress or defects in the overlying SOI layers and resultant degradation of device performance. It is therefore essential to establish the quality of the silicon on the GPSOI substrate. MOS capacitor structures have been employed in this paper to characterize these GPSOI substrates for the first time. High quality MOS capacitor characteristics have been achieved with minority carrier lifetime of similar to 0.8 ms. These results show that the substrate is suitable for device manufacture with no degradation in the silicon due to stress or metallic contamination resulting from the inclusion of the underlying silicide layer.

Electrical characterization of ALD Al2O3 and HfO2 films on germanium

Al2O3 and HfO2 films were deposited on germanium substrates by atomic layer deposition (ALD) and analyzed by MOS capacitor electrical characterization. In-situ plasma nitridation performed prior to ALD was found to improve the stability of the interface. For Al 2O3/GeON/Ge capacitors, a 450°C anneal in nitrogen ambient reduced hysteresis and oxide fixed charge to 90 mV and 1012 cm-2 respectively, with low leakage current density. On the contrary, degradation was observed for un-nitrided Al2O3/Ge capacitors after 300 and 400°C post-metal anneals. HfO2/GeON/Ge capacitors benefitted from a 400°C densification anneal but exhibited degradation after post-metal anneals at temperatures greater than 300°C. This degradation is attributed to the influence of Al electrodes on the HfO 2 gate stack. HfO2 is considered to be a suitable material for the gate stack and Al2O3 for the buried dielectric in a GeOI structure. ©The Electrochemical Society.

Germanium MOS Capacitors with Hafnium Dioxide and Silicon Dioxide Dielectrics

Germanium (Ge) does not grow a suitable oxide for MOS devices. The Ge/dielectric interface is of prime importance to the operation of photo-detectors and scaled MOSTs. Therefore there is a requirement for deposited or bonded dielectric materials. MOS capacitors have been formed on germanium substrates with three different dielectric materials. Firstly, a thermally grown and bonded silicon dioxide (SiO2) layer, secondly, SiO2 deposited by atmospheric pressure CVD ‘silox’, and thirdly a hafnium oxide (HfO2) high-k dielectric deposited by atomic layer deposition (ALD). Ge wafers used were p-type 1 0 0 2 O cm. C–V measurements have been made on all three types of capacitors to assess the interface quality. ALD HfO2 and silox both display acceptable C–V characteristics. Threshold voltage and maximum and minimum capacitance values closely match expected values found through calculation. However, the bonded SiO2 has non-ideal C–V characteristics, revealing the presence of a high density of interface states. A H2/N2 post metal anneal has a detrimental effect on C–V characteristics of HfO2 and silox dielectrics, causing a shift in the threshold voltage and rise in the minimum capacitance value. In the case of hafnium dioxide, capacitor properties can be improved by performing a plasma nitridation of the Ge surface prior to dielectric deposition.

Low temperature surface nitridation processes for dielectric-Ge interfaces

Germanium MOS capacitors have been fabricated with a high-? HfO dielectric using ALD. An in-situ low temperature (250°C) nitrogen plasma treatment on the germanium surface prior to the deposition of HfO was found to be beneficial to the electrical properties of the devices. Germanium MOS capacitors have also been fabricated with a SiO dielectric deposited by an atmospheric pressure CVD 'silox' process. The same low temperature plasma nitridation was found to degrade the electrical properties of the silox devices. The effect of a post-metal anneal in H and N on both types of capacitor structure was also found to degrade device electrical properties. copyright The Electrochemical Society.

Comparative analysis of nanoscale MOS device architectures for RF applications

This paper provides valuable design insights for optimizing device parameters for nanoscale planar and vertical SOI MOSFETs. The suitability of nanoscale non-planar FinFETs and classical planar single and double gate SOI MOSFETs for rf applications is examined via extensive 3D device simulations and detailed interpretation. The origin of higher parasitic capacitance in FinFETs, compared to planar MOSFETs is examined. RF figures of merit for planar and vertical MOS devices are compared, based on layout-area calculations.

Toward Self-Assembled Ferroelectric Random Access Memories: Hard-Wired Switching Capacitor Arrays with Almost Tb/in.2 Densities

We report on the successful fabrication of arrays of switchable nanocapacitors made by harnessing the self-assembly of materials. The structures are composed of arrays of 20-40 nm diameter Pt nanowires, spaced 50-100 nm apart, electrodeposited through nanoporous alumina onto a thin film lower electrode on a silicon wafer. A thin film ferroelectric (both barium titanate (BTO) and lead zirconium titanate (PZT)) has been deposited on top of the nanowire array, followed by the deposition of thin film upper electrodes. The PZT nanocapacitors exhibit hysteresis loops with substantial remnant polarizations, while although the switching performance was inferior, the low-field characteristics of the BTO nanocapacitors show dielectric behavior comparable to conventional thin film heterostructures. While registration is not sufficient for commercial RAM production, this is nevertheless an embryonic form of the highest density hard-wired FRAM capacitor array reported to date and compares favorably with atomic force microscopy read-write densities.

Thin film capacitor cut from single crystals using focused ion beam milling

The focused ion beam microscope (FIB) has been used to fabricate thin parallel-sided ferroelectric capacitors from single crystals of BaTiO3 and SrTiO3. A series of nano-sized capacitors ranging in thickness from similar to660 nm to similar to300 nm were made. Cross-sectional high resolution transmission electron microscopy (HRTEM) revealed that during capacitor fabrication, the FIB rendered around 20 nm of dielectric at the electrode-dielectric interface amorphous, associated with local gallium impregnation. Such a region would act electrically in series with the single crystal and would presumably have a considerable negative influence on the dielectric properties. However, thermal annealing prior to gold electrodes deposition was found to fully recover the single crystal capacitors and homogenise the gallium profile. The dielectric testing of the STO ultra-thin single crystal capacitors was performed yielding a room temperature dielectric constant of similar to300, as is the case in bulk. Therefore, there was no evidence of a collapse in dielectric constant associated with thin film dimensions.