In situ preparation of 3D graphene aerogels@hierarchical Fe3O4 nanoclusters as high rate and long cycle anode materials for lithium ion batteries

We describe a novel strategy for in situ fabrication of hierarchical Fe₃O₄ nanoclusters-GAs. Fe₃O₄ NCs-GAs deliver excellent rate capability (the reversible capacities obtained were 1442, 392 and 118 mA h g^-1 at 0.1C, 12C and 35C rates), and a high reversible capacity of 577 mA h g^-1 over 300 cycles at the current density of 5.2 A g^-1 (6C).

In situ synthesis of LiV3O8 nanorods on graphene as high rate-performance cathode materials for rechargeable lithium batteries

We developed a facile two-step hydrothermal procedure to prepare hybrid materials of LiV₃O₈ nanorods on graphene sheets. The special structure endows them with the high-rate transportation of electrolyte ions and electrons throughout the electrode matrix, resulting in remarkable electrochemical performance when they were used as cathodes in rechargeable lithium batteries. © 2013 The Royal Society of Chemistry.

A Phase-field Model for Computer Simulation of Lamellar Structure Formation in y-TiAI

In the present paper, a phase-field model is developed to simulate the formation and evolution of lamellar microstructure in γ-TiAl alloys. The mechanism of formation of TiAl lamellae proposed by Denquin and Naka is incorporated into the model. The model describes the formation and evolution of the face-centered cubic (fcc) stacking lamellar zone followed by the subsequent appearance and growth of the γ-phase, involving both the chemical composition change by atom transfer and the ordering of the fcc lattice. The thermodynamics of the model system and the interaction between the displacive and diffusional transformations are described by a non-equilibrium free energy formulated as a function of concentration and structural order parameter fields. The long-range elastic interactions, arising from the lattice misfit between the α, fcc (A1) and the various orientation variants of the γ-phase are taken into account by incorporating of the elastic strain energy into the total free energy. Simulation studies based on the model successfully predicted some essential features of the lamellar structure. It is found that the formation and evolution of the lamellar structure are predominantly controlled by the minimization of the elastic energy of the interfaces between the different fcc stacking groups, low-symmetry product phase γ and the high-symmetry α-phase, as well as between the various orientation variants of the product phase.

LPCVD of tungsten by selective deposition on silicon

Beta-phase W, selectively grown at 440C had resistivity 20 micro-ohm cm and maximum layer thickness 100nm. Hydrogen passivation proved essential in this process. Higher deposition temperatures resulted in increased layer thickness but incorporated WSi2 and alpha- phase W. Self limiting W grown on polycrystalline and heavily doped silicon yielded reduced thickness. Boron is involved in the WF6 reduction reaction but phosphorus is not and becomes incorporated in the W layer. The paper establishes an optimised and novel CVD process suited to IC contact technology. A funded technology transfer contract with National Semiconductor Greenock (M Fallon) resulted from this work.

Tungsten Silicide Contacts to Polycrystalline Silicon and Silicon-Germanium Alloys

Novel CVD WSi2 technology with low series and contact resistance in SiGe HBTs was achieved. Specific contact resistance to Si1-xGex with 0

Parameter sensitivity for optimal design of 65 nm node SOI transistors

Mixed-mode simulation, where device simulation is embedded directly within a circuit simulator, is used for the first time to provide scaling guidelines to achieve optimal digital circuit performance for double gate SOI MOSFETs. This significant advance overcomes the lack of availability of SPICE model parameters. The sensitivity of the gate delay and on-off current ratio to each of the key geometric and technological parameters of the transistor is quantified. The impact of the source-drain doping profile on circuit performance is comprehensively investigated.

Optimisation of source/drain extension region profile for suppression of short channel effects in sub-50 nm DG SOI MOSFETs with high- k gate dielectrics

Novel technology dependent scaling parameters i.e. spacer to gradient ratio and effective channel length (Leff) are proposed for source/drain engineered DG MOSFET, and their significance in minimizing short channel effects (SCES) in high-k gate dielectrics is discussed in detail. Results show that a high-k dielectric should be associated with a higher spacer to gradient ratio to minimise SCEs The analytical model agrees with simulated data over the entire range of spacer widths, doping gradients, high-k gate dielectrics and effective channel lengths.

Performance assessment of nanoscale double- and triple- gate FinFETs

This is the first paper to describe performance assessment of triple and double gate FinFETs for High Performance (HP), Low Operating Power (LOP) and Low Standby Power (LSTP) logic technologies is investigated. The impact of gate work-function, spacer width, lateral source/drain doping gradient, fin aspect ratio, fin thickness on device performance, has been analysed in detail and guidelines are presented to meet ITRS specification at 65 and 45 nm nodes. Optimal design of lateral source/drain doping profile can not only effectively control short channel effects, yielding low off-current, but also achieve low values of intrinsic gate delay.