Surface-Potential-Based Drain Current Analytical Model for Triple-Gate Junctionless Nanowire Transistors

This paper proposes a drain current model for triple-gate n-type junctionless nanowire transistors. The model is based on the solution of the Poisson equation. First, the 2-D Poisson equation is used to obtain the effective surface potential for long-channel devices, which is used to calculate the charge density along the channel and the drain current. The solution of the 3-D Laplace equation is added to the 2-D model in order to account for the short-channel effects. The proposed model is validated using 3-D TCAD simulations where the drain current and its derivatives, the potential, and the charge density have been compared, showing a good agreement for all parameters. Experimental data of short- channel devices down to 30 nm at different temperatures have been also used to validate the model.

A novel self consistent calculation approach for the capacitance-voltage characteristics of semiconductor quantum wire transistors based on a split-gate configuration

Purpose - The purpose of this paper is to develop an efficient numerical algorithm for the self-consistent solution of Schrodinger and Poisson equations in one-dimensional systems. The goal is to compute the charge-control and capacitance-voltage characteristics of quantum wire transistors. Design/methodology/approach - The paper presents a numerical formulation employing a non-uniform finite difference discretization scheme, in which the wavefunctions and electronic energy levels are obtained by solving the Schrodinger equation through the split-operator method while a relaxation method in the FTCS scheme ("Forward Time Centered Space") is used to solve the two-dimensional Poisson equation. Findings - The numerical model is validated by taking previously published results as a benchmark and then applying them to yield the charge-control characteristics and the capacitance-voltage relationship for a split-gate quantum wire device. Originality/value - The paper helps to fulfill the need for C-V models of quantum wire device. To do so, the authors implemented a straightforward calculation method for the two-dimensional electronic carrier density n(x,y). The formulation reduces the computational procedure to a much simpler problem, similar to the one-dimensional quantization case, significantly diminishing running time.

Comparative study of the proton beam effects between the conventional and Circular-Gate MOSFETs

The study of ionizing radiation effects on semiconductor devices is of great relevance for the global technological development and is a necessity in some strategic areas in Brazil. This work presents preliminary results of radiation effects in MOSFETs that were exposed to 3.2 Grad radiation dose produced by a 2.6-MeV proton beam. The focus of this work was to electrically characterize a Rectangular-Gate MOSFET (RGT) and a Circular-Gate MOSFET (CGT), manufactured with the On Semiconductor 0.5 mu m standard CMOS fabrication process and to verify a suitable geometry for space applications. During the experiment, I-DS x V-GS curves were measured. After irradiation, the RGT off-state current (I-OFF) increased approximately two orders of magnitude reaching practically the same value of the I-OFF in the CGT, which only doubled its value. (C) 2011 Elsevier B.V. All rights reserved.

An analytic method to compute the stress dependence on the dimensions and its influence in the characteristics of triple gate devices

Triple-gate devices are considered a promising solution for sub-20 nm era. Strain engineering has also been recognized as an alternative due to the increase in the carriers mobility it propitiates. The simulation of strained devices has the major drawback of the stress non-uniformity, which cannot be easily considered in a device TCAD simulation without the coupled process simulation that is time consuming and cumbersome task. However, it is mandatory to have accurate device simulation, with good correlation with experimental results of strained devices, allowing for in-depth physical insight as well as prediction on the stress impact on the device electrical characteristics. This work proposes the use of an analytic function, based on the literature, to describe accurately the strain dependence on both channel length and fin width in order to simulate adequately strained triple-gate devices. The maximum transconductance and the threshold voltage are used as the key parameters to compare simulated and experimental data. The results show the agreement of the proposed analytic function with the experimental results. Also, an analysis on the threshold voltage variation is carried out, showing that the stress affects the dependence of the threshold voltage on the temperature. (C) 2011 Elsevier Ltd. All rights reserved.

Dendrimers/TiO2 nanoparticles layer-by-layer films as extended gate FET for pH detection

The layer-by-layer (LbL) technique combined with field-effect transistor (FET) based sensors has enabled the production of pH-sensitive platforms with potential application in biosensors. A variation of the FET architecture, so called separative extended gate FET (SEGFET) devices, are promise as an alternative to conventional ion sensitive FET (ISFET). SEGFET configuration exhibits the advantage of combining the field-effect concept with organic and inorganic materials directly adsorbed on the extended gate, allowing the test of new pH-sensitive materials in a simple and low cost way. In this communication, poly(propylene imine) dendrimer (PPI) and TiO2 nanoparticles (TiO2-np) were assembled onto gold-covered substrates via layer-by-layer technique to produce a low cost SEGFET pH sensor. The sensor presented good pH sensitivity, ca. 57 mV pH(-1), showing that our strategy has potential advantages to fabricate low cost pH-sensing membranes. (C) 2012 Elsevier B.V. All rights reserved.

The Dependence of Retention Time on Gate Length in UTBOX FBRAM With Different Source/Drain Junction Engineering

The floating-body-RAM sense margin and retention-time dependence on the gate length is investigated in UTBOX devices using BJT programming combined with a positive back bias (so-called V th feedback). It is shown that the sense margin and the retention time can be kept constant versus the gate length by using a positive back bias. Nevertheless, below a critical L, there is no room for optimization, and the memory performances suddenly drop. The mechanism behind this degradation is attributed to GIDL current amplification by the lateral bipolar transistor with a narrow base. The gate length can be further scaled using underlap junctions.

Behavior of triple-gate Bulk FinFETs with and without DTMOS operation

In this paper, the combination of the Dynamic Threshold (DT) voltage technique with a non-planar structure is experimentally studied in triple-gate FinFETs. The drain current, transconductance, resistance, threshold voltage, subthreshold swing and Drain Induced Barrier Lowering (DIBL) will be analyzed in the DT mode and the standard biasing configuration. Moreover, for the first time, the important figures of merit for the analog performance such as transconductance-over-drain current, output conductance. Early voltage and intrinsic voltage gain will be studied experimentally and through three-dimensional (3-D) numerical simulations for different channel doping concentrations in triple-gate DTMOS FinFETs. The results indicate that the DTMOS FinFETs always yield superior characteristic; and larger transistor efficiency. In addition, DTMOS devices with a high channel doping concentration exhibit much better analog performance compared to the normal operation mode, which is desirable for high performance low-power/low-voltage applications. (C) 2011 Elsevier Ltd. All rights reserved.

Dependence of Generation-Recombination Noise With Gate Voltage in FD SOI MOSFETs

A model for computing the generation-recombination noise due to traps within the semiconductor film of fully depleted silicon-on-insulator MOSFET transistors is presented. Dependence of the corner frequency of the Lorentzian spectra on the gate voltage is addressed in this paper, which is different to the constant behavior expected for bulk transistors. The shift in the corner frequency makes the characterization process easier. It helps to identify the energy position, capture cross sections, and densities of the traps. This characterization task is carried out considering noise measurements of two different candidate structures for single-transistor dynamic random access memory devices.

Analysis of temperature variation influence on the analog performance of 45 degrees rotated triple-gate nMuGFETs

This work presents the analog performance of n-type triple-gate MuGFETs with high-k dielectrics and TiN gate material fabricated in 45 degrees rotated SOI substrates comparing their performance with standard MuGFETs fabricated without substrate rotation. Different fin widths are studied for temperatures ranging from 250 K up to 400 K. The results of transconductance, output conductance, transconductance over drain current ratio, intrinsic voltage gain and unit-gain frequency are studied. It is observed that the substrate rotation improves the carrier mobility of narrow MuGFETs at any temperature because of the changing in the conduction plane at the sidewalls from (1 1 0) to (1 0 0). For lower temperatures, the improvement of the carrier mobility of rotated MuGFETs is more noticeable as well as the rate of mobility improvement with the temperature decrease is larger. The output conductance is weakly affected by the substrate rotation. Although this improvement in the transconductance of rotated MuGFETs is negligibly transferred to the intrinsic voltage gain, the unity-gain frequency of rotated device is improved due to the larger carrier mobility in the entire range of temperatures studied. (C) 2011 Elsevier Ltd. All rights reserved.

GIDL behavior of p- and n-MuGFET devices with different TiN metal gate thickness and high-k gate dielectrics

This work studies the gate-induced drain leakage (GIDL) in p- and n-MuGFET structures with different TiN metal gate thickness and high-k gate dielectrics. As a result of this analysis, it was observed that a thinner TiN metal gate showed a larger GIDL due to the different gate oxide thickness and a reduced metal gate work function. In addition, replacing SiON by a high-k dielectric (HfSiON) results for nMuGFETs in a decrease of the GIDL On the other hand, the impact of the gate dielectric on the GIDL for p-channel MuGFETs is marginal. The effect of the channel width was also studied, whereby narrow fin devices exhibit a reduced GIDL current in spite of the larger vertical electric field expected for these devices. Finally, comparing the effect of the channel type, an enhanced GIDL current for pMuGFET devices was observed. (C) 2011 Elsevier Ltd. All rights reserved.

Exact dynamics of single-qubit-gate fidelities under the measurement-based quantum computation scheme

Measurement-based quantum computation is an efficient model to perform universal computation. Nevertheless, theoretical questions have been raised, mainly with respect to realistic noise conditions. In order to shed some light on this issue, we evaluate the exact dynamics of some single-qubit-gate fidelities using the measurement-based quantum computation scheme when the qubits which are used as a resource interact with a common dephasing environment. We report a necessary condition for the fidelity dynamics of a general pure N-qubit state, interacting with this type of error channel, to present an oscillatory behavior, and we show that for the initial canonical cluster state, the fidelity oscillates as a function of time. This state fidelity oscillatory behavior brings significant variations to the values of the computational results of a generic gate acting on that state depending on the instants we choose to apply our set of projective measurements. As we shall see, considering some specific gates that are frequently found in the literature, the fast application of the set of projective measurements does not necessarily imply high gate fidelity, and likewise the slow application thereof does not necessarily imply low gate fidelity. Our condition for the occurrence of the fidelity oscillatory behavior shows that the oscillation presented by the cluster state is due exclusively to its initial geometry. Other states that can be used as resources for measurement-based quantum computation can present the same initial geometrical condition. Therefore, it is very important for the present scheme to know when the fidelity of a particular resource state will oscillate in time and, if this is the case, what are the best times to perform the measurements.

Raman and XRD study on brookite-anatase coexistence in cathodic electrosynthesized titania

Among the many methods developed for the synthesis of titanium dioxide, cathodic electrosynthesis has not received much attention because the resulting amorphous oxy-hydroxide matrix demands a further thermal annealing step to be transformed into crystalline titania. However, the possibility of filling deep recessed templates by the control of the solidliquid interface makes it a potentially suitable technique for the fabrication of porous scaffolds for photovoltaics and photocatalysis. Furthermore, a careful control of the crystallization process enables the growth of larger grains with lower density of grain boundaries, which act as electron traps that slow down electronic transport and promote charge recombination. In this report, well crystallized titania deposits were obtained by thermal annealing of amorphous deposits fabricated by cathodically assisted electrosynthesis on indium-tin oxide (ITO)substrates. The combined use of Raman spectroscopy and X-ray diffraction showed that the crystallization process is more intricate than previously assumed. It is shown that the amorphous matrix evolves into a rutile-free mixture of brookite and anatase at temperatures as low as 200 degrees C that persists up to 800 degrees C, when pure anatase dominates. The amount of brookite in the brookiteanatase mixture reaches a maximum at 400 degrees C. This very simple method for obtaining a brookiteanatase mixture and the ability to tune their proportions by thermal annealing is a promising alternative whose potential for solar cells and photocatalysis deserves a careful evaluation. Copyright (C) 2011 John Wiley & Sons, Ltd.

Ion-sensing properties of 1D vanadium pentoxide nanostructures

The application of one-dimensional (1D) V2O5 center dot nH(2)O nanostructures as pH sensing material was evaluated. 1D V2O5 center dot nH(2)O nanostructures were obtained by a hydrothermal method with systematic control of morphology forming different nanostructures: nanoribbons, nanowires and nanorods. Deposited onto Au-covered substrates, 1D V2O5 center dot nH(2)O nanostructures were employed as gate material in pH sensors based on separative extended gate FET as an alternative to provide FET isolation from the chemical environment. 1D V2O5 center dot nH(2)O nanostructures showed pH sensitivity around the expected theoretical value. Due to high pH sensing properties, flexibility and low cost, further applications of 1D V2O5 center dot nH(2)O nanostructures comprise enzyme FET-based biosensors using immobilized enzymes.

Redox Control of 20S Proteasome Gating

The proteasome is the primary contributor in intracellular proteolysis. Oxidized or unstructured proteins can be degraded via a ubiquitin-and ATP-independent process by the free 20S proteasome (20SPT). The mechanism by which these proteins enter the catalytic chamber is not understood thus far, although the 20SPT gating conformation is considered to be an important barrier to allowing proteins free entrance. We have previously shown that S-glutathiolation of the 20SPT is a post-translational modification affecting the proteasomal activities. Aims: The goal of this work was to investigate the mechanism that regulates 20SPT activity, which includes the identification of the Cys residues prone to S-glutathiolation. Results: Modulation of 20SPT activity by proteasome gating is at least partially due to the S-glutathiolation of specific Cys residues. The gate was open when the 20SPT was S-glutathiolated, whereas following treatment with high concentrations of dithiothreitol, the gate was closed. S-glutathiolated 20SPT was more effective at degrading both oxidized and partially unfolded proteins than its reduced form. Only 2 out of 28 Cys were observed to be S-glutathiolated in the proteasomal alpha 5 subunit of yeast cells grown to the stationary phase in glucose-containing medium. Innovation: We demonstrate a redox post-translational regulatory mechanism controlling 20SPT activity. Conclusion: S-glutathiolation is a post-translational modification that triggers gate opening and thereby activates the proteolytic activities of free 20SPT. This process appears to be an important regulatory mechanism to intensify the removal of oxidized or unstructured proteins in stressful situations by a process independent of ubiquitination and ATP consumption. Antioxid. Redox Signal. 16, 1183-1194.

Junction Field Effect on the Retention Time for One-Transistor Floating-Body RAM

One-transistor floating-body random access memory retention time distribution is investigated on silicon-on-insulator UTBOX devices. It is shown that the average retention time can be improved by two to three orders of magnitude by reducing the body-junction electric field. However, the retention time distribution, which is mainly caused by the generation-recombination center density variation, remains similar.