The Dependence of Retention Time on Gate Length in UTBOX FBRAM With Different Source/Drain Junction Engineering
| Contribuinte(s) |
UNIVERSIDADE DE SÃO PAULO |
|---|---|
| Data(s) |
05/11/2013
05/11/2013
2012
|
| Resumo |
The floating-body-RAM sense margin and retention-time dependence on the gate length is investigated in UTBOX devices using BJT programming combined with a positive back bias (so-called V th feedback). It is shown that the sense margin and the retention time can be kept constant versus the gate length by using a positive back bias. Nevertheless, below a critical L, there is no room for optimization, and the memory performances suddenly drop. The mechanism behind this degradation is attributed to GIDL current amplification by the lateral bipolar transistor with a narrow base. The gate length can be further scaled using underlap junctions. Brazilian research-funding agency CAPES Brazilian research funding agency CAPES CNPq CNPq |
| Identificador |
IEEE ELECTRON DEVICE LETTERS, PISCATAWAY, v. 33, n. 7, supl. 1, Part 1, pp. 940-942, JUL, 2012 0741-3106 http://www.producao.usp.br/handle/BDPI/41217 10.1109/LED.2012.2196968 |
| Idioma(s) |
eng |
| Publicador |
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC PISCATAWAY |
| Relação |
IEEE ELECTRON DEVICE LETTERS |
| Direitos |
restrictedAccess Copyright IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC |
| Palavras-Chave | #RETENTION TIME #SCALABILITY #SENSE MARGIN #UNDERLAP #UTBOX #1T-FLOATING-BODY RAM (FBRAM) #DRAIN-LEAKAGE GIDL #ENGINEERING, ELECTRICAL & ELECTRONIC |
| Tipo |
article original article publishedVersion |
