A low power integrated CMOS transmitter for BCI system

The prototype wafer of a low power integrated CMOS Transmitter for short-range biotelemetry application has been designed and fabricated, which is prospective to be implanted in the human brain to transfer the extracted neural information to the external computer. The transmitter consists of five parts, a bandgap current regulator, a ring oscillator, a buffer, a modulator and a power transistor. High integration and low power are the most distinct criteria for such an implantable integrated circuit. The post-simulation results show that under a 3.3 V power supply the transmitter provides 100.1 MHz half-wave sinusoid current signal to drive the off-chip antenna, the output peak current range is -0.155 mA similar to 1.250 mA, and on-chip static power dissipation is low to 0.374 mW. All the performances of the transmitter satisfy the demands of wireless real-time BCI system for neural signals recording and processing.

The improvement of thick oxidized porous silicon layer growth process - art. no. 60290S

Oxidizing thick porous silicon layer into silicon dioxide is a timesaving and low-cost process for producing thick silicon dioxide layer used in silicon-based optical waveguide devices. The solution of H2O2 is proposed to post-treat thick porous silicon (PS) films. The prepared PS layer as the cathode is applied about 10 mA/cm(2) current in mixture of ethanol, HF, and H2O2 solutions, in order to improve the stability and the smoothness of the surface. With the low-temperature dry-O-2 pre-oxidizations and high-temperature wet O-2 oxidizations process, a high-quality SiO2 30 mu m thickness layer that fit for the optical waveguide device was prepared. The SEM images show significant improved smoothness on the surface of oxidized PS thick films, the SiO2 film has a stable and uniformity reflex index that measured by the prism coupler, the uniformity of the reflex index in different place of the wafer is about 0.0003.

Recent progresses of SOI-based photonic devices - art. no. 60201R

SOI (Silicon on Insulator) based photonic devices, including stimulated emission from Si diode, RCE (Resonant Cavity Enhanced) photodiode with quantum structure, MOS (Metal Oxide Semiconductor) optical modulator with high frequency, SOI optical matrix switch and wavelength tunable filter are reviewed in the paper. The emphasis will be played on our recent results of SOI-based thermo-optic waveguide matrix switch with low insertion loss and fast response. A folding re-arrangeable non-blocking 4x4 matrix switch with total internal reflection (TIR) mirrors and a first blocking 16 x 16 matrix were fabricated on SOI wafer. The extinction ratio and the crosstalk are better. The insertion loss and the polarization dependent loss (PDL) at 1.55 mu m increase slightly with longer device length and more bend and intersecting waveguides. The insertion losses are expected to decrease 2-3 dB when anti-reflection films are added in the ends of the devices. The rise and fall times of the devices are 2.1 mu s and 2.3 mu s, respectively.

Shallow donor defect formation and its influence on semi-insulating indium phosphide after high temperature annealing with long duration

Fe-doped semi-insulating (SI) InP has become semi-conducting (SC) material completely after annealing at 900 V for 10 hours. Defects in the SC and SI InP materials have been studied by deep level transient spectroscopy (DLTS) and thermally stimulated current spectroscopy (TSC) respectively. The DLTS only detected Fe acceptor related deep level defect with significant concentration, suggesting the formation of a high concentration of shallow donor in the SC-InP TSC results confirmed the nonexistence of deep level defects in the annealed SI-InP. The results demonstrate a significant influence of the thermally induced defects on the electrical properties of SI-InP. The formation mechanism and the nature of the shallow donor defect have been discussed based on the results.

1.55-mu m resonant cavity enhanced photodiode based on MBE grown Ge quantum dots

Self-assembly Ge quantum dots (QD) on Si and Si/Ge mutli-quantum-wells (MQW) are grown by MBE. The island size and island density was investigated by atomics force microscopy. Ten-layer and twenty-layer MQW were selected for photodiode device fabrication. In photoluminescence (PL), a broad peak around 1.55-mu m wavelength was observed with higher peak intensity for the 10-layer MQW which had less defects than the 20-layer sample. Resonant cavity enhanced (RCE) photodiodes were fabricated by bonding on a SOI wafer. Selected responsivity at 1.55 mu m was successfully demonstrated. (c) 2005 Elsevier B.V. All rights reserved.

Growth of ZnO single crystal by chemical vapor transport method

ZnO crystals were grown by CVT method in closed quartz tube under seeded condition. Carbon was used as a transport agent to enhance the chemical transport of ZnO in the growth process. ZnO single crystals were grown by using GaN/sapphire and GaN/Si wafer as seeds. The property and crystal quality of the ZnO single crystals was studied by photoluminescence spectroscopy and X-ray diffraction technique.

Compact polarization-insensitive arrayed waveguide grating based on SOI material

A compact polarization-insensitive 8x8 arrayed waveguide grating with 100GHz channel spacing at 1.55 mu m is presented on the material of silicon on insulator (SOI). Increasing the epitaxial layer thickness can reduce the birefringence of the waveguide, but the wvaeguide's bend radius also increases at the same time. We choose the SOI wafer with 3.0 mu m epitaxial layer to reduce the device's size and designed the appropriate structure of rib wave-guides to eliminate the polarization dependant wavelength shift. Compared to the other methods of eliminating the polarization dependant wavelength shift, the method is convenient and easy to control the polarization without additional etching process. The index differences between TE0 and TM0 of straight and bend waveguides are 1.4x10(-5) and 3.9x10(-5), respectively. The results showed that the polarization dependant wavelength shift is 0.1nm, and the device size is 1.5x1.0 cm(2).

Selective and lithography-independent fabrication of 20 nm nano-gap electrodes and nano-channels for nanoelectrofluidics applications

A new method has been developed to selectively fabricate nano-gap electrodes and nano-channels by conventional lithography. Based on a sacrificial spacer process, we have successfully obtained sub-100-nm nano-gap electrodes and nano-channels and further reduced the dimensions to 20 nm by shrinking the sacrificial spacer size. Our method shows good selectivity between nano-gap electrodes and nano-channels due to different sacrificial spacer etch conditions. There is no length limit for the nano-gap electrode and the nano-channel. The method reported in this paper also allows for wafer scale fabrication, high throughput, low cost, and good compatibility with modern semiconductor technology.

EXCIMER-LASER DOPING OF SPIN-ON DOPANT IN SILICON

Solid films containing phosphorus impurities were formed on p-type silicon wafer surface by traditional spin-on of commercially available dopants. The doping process is accomplished by irradiating the sample with a 308 nm XeCl pulsed excimer laser. Shallow junctions with a high concentration of doped impurities were obtained. The measured impurity profile was ''box-like'', and is very suitable for use in VLSI devices. The characteristics of the doping profile against laser fluence (energy density) and number of laser pulses were studied. From these results, it is found that the sheet resistance decreases with the laser fluence above a certain threshold, but it saturates as the energy density is further increased. The junction depth increases with the number of pulses and the laser energy density. The results suggest that this simple spin-on dopant pre-deposition technique can be used to obtain a well controlled doping profile similar to the technique using chemical vapor in pulsed laser doping process.

A COMPARATIVELY LOW-QUALITY SILICON MATERIAL IMPROVED FOR SOLAR-CELL FABRICATION

A comparatively low-quality silicon wafer (with a purity of almost-equal-to 99.9%) was adopted to form a silicon-on-defect-layer (SODL) structure featuring improved crystalline silicon near the defect layer (DL) by means of proton implantation and subsequent annealing. Thus, the SODL technique provides an opportunity to enable low-quality silicon wafers to be used for fabrication of low-cost solar cells.

Polycrystalline silicon thin films and solar cells prepared by rapid thermal CVD

Polycrystalline silicon (poly-Si) films(similar to 10 mu m) were grown from dichlorosilane by a rapid thermal chemical vapor deposition (RTCVD) technique, with a growth rate up to 100 Angstrom/s at the substrate temperature (T-s) of 1030 degrees C. The average grain size and carrier mobility of the films were found to be dependent on the substrate temperature and material. By using the poly-Si films, the first model pn(+) junction solar cell without anti-reflecting (AR) coating has been prepared on an unpolished heavily phosphorus-doped Si wafer, with an energy conversion efficiency of 4.54% (AM 1.5, 100 mW/cm(2), 1 cm(2)).

Growth of high-quality relaxed In0.3Ga0.7As/GaAs superlattices

With a low strained InxGa1-xAs/GaAs(x similar to 0.01) superlattice (SL) buffer layer, the crystal quality of 50 period relaxed In0.3Ga0.7As/GaAs strained SLs has been greatly improved and over 13 satellite peaks are observed from X-ray double-crystal diffraction, compared with three peaks in the sample without the buffer layer. Cross-section transmission electron microscopy reveals that the dislocations due to superlattice strain relaxation are blocked by the SLs itself and are buried into the buffer layer. The role of the SL buffer layer lies in that the number of the dislocations is reduced in two ways: (1) the island formation is avoided and (2) the initial nucleation of the threading dislocations is retarded by the high-quality growth of the SL buffer layer. When the dislocation pinning becomes weak as a result of the reduced dislocation density, the SLs can effectively move the threading dislocations to the edge of the wafer.

Stoichiometric defects in semi-insulating GaAs

The influences of arsenic interstitials and dislocations on the lattice parameters of undoped semi-insulating (SI) GaAs single crystals were analyzed. It was shown that the dislocations in such crystals serve as effective gettering sites for arsenic interstitials due to the deformation energy of dislocations. The average excess arsenic in GaAs epilayers grown by molecular-beam epitaxy (MBE) at low temperatures (LT) is about 1%, and the lattice parameters of these epilayers are larger than those of liquid-encapsulated Czochralski-grown (LEG) SI-GaAs by about 0.1%. The atomic ratio, [As]/([Ga] + [As]), in SI-GaAs grown by low-pressure (LP) LEC is the nearest to the strict stoichiometry compared with those grown by high-pressure (HP) LEC and vertical gradient freeze (VGF). After multiple wafer annealing (MWA), the crystals grown by HPLEC become closer to be strictly stoichiometric.

High efficiency AlxGa1-xAs/GaAs solar cells: Fabrication, irradiation and annealing effect

High efficiency AlxGa1-xAs/GaAs heteroface solar cells have been fabricated by an improved multi-wafer squeezing graphite boat liquid phase epitaxy (LPE) technique, which enables simultaneous growth of twenty 2.3 X 2.3cm(2) epilayers in one run. A total area conversion efficiency of 17.33% is exhibited (1sun, AM0, 2.0 x 2.0cm(2)). The shallow junction cell shows more resistance to 1 MeV electron radiation than the deep one. After isochronal or isothermal annealing the density and the number of deep level traps induced by irradiation are reduced effectively for the solar cells with deep junction and bombardment under high electron fluences.

Lithography-independent and large scale fabrication of a metal electrode nanogap

A lithography-independent and wafer scale method to fabricate a metal nanogap structure is demon-strated. Polysilicon was first dry etched using photoresist (PR) as the etch mask patterned by photolithography.Then, by depositing conformal SiO_2 on the polysilicon pattern, etching back SiO_2 anisotropically in the perpendic-ular direction and removing the polysilicon with KOH, a sacrificial SiO_2 spacer was obtained. Finally, after metal evaporation and lifting-off of the SiO_2 spacer, an 82 nm metal-gap structure was achieved. The size of the nanogap is not determined by the photolithography, but by the thickness of the SiO_2. The method reported in this paper is compatible with modern semiconductor technology and can be used in mass production.