Multimode-interference-type thermo-optic variable optical attenuator with a response frequency of 10 kHz

A thermo-optic variable optical attenuator based on a multimode interference coupler principle is fabricated. The propagation loss of the fabricated device is 1.6 to 3.8 dB at the wavelength range 1510 to 1610 nm, which is very near the calculated value (1.2 dB) by the finite difference beam propagation method. The maximum power consumption is 363 mW and the dynamic attenuation range is 0 to 26 dB. The response frequency of the fabricated attenuator is about 10 kHz. (C) 2003 Society of Photo-Optical Instrumentation Engineers.

Anomaly of the current self-oscillation frequency in the sequential tunneling of a doped GaAs/AlAs superlattice

An anomalous behavior of the current self-oscillation frequency is observed in the dynamic de voltage bands, emerging from each sawtoothlike branch of the current-voltage characteristic of a doped GaAs/A1As superlattice in the transition process from static to dynamic electric field domain formations. Varying the applied de voltage at a fixed temperature, we find that the frequency increases while the averaged current decreases. Inside each voltage band, the frequency has a strong voltage dependence in the temperature range where the averaged current changes with the applied de voltage. This dependence can be understood in terms of motion of the system along a limit cycle.

High-frequency hydrogen-related infrared modes in silicon grown in a hydrogen atmosphere

High-frequency vibrational modes have been observed at liquid-helium temperature in silicon samples grown in a H-2 or D-2 atmosphere. The highest-frequency ones are due to the overtones and combination modes of SiH fundamentals. Others are CH modes due to (C,H) complexes, but the simultaneous presence of NH modes due to (N,H) complexes cannot be excluded. The present results seem to show also the existence of centers including both SiH and CH or NH bonds. One sharp mode at 4349 cm-l is related to a weak SiH fundamental at 2210 cm(-1). The related center is ascribed to a vacancy fully decorated with hydrogen with a nearest-neighbor C atom. [S0163-1829(99)00911-X].

High-frequency ferromagnetic resonance on ultrafine cobalt particles

We report on high-frequency (300-700 GHz) ferromagnetic resonance (HF-FMR) measurements on cobalt superparamagnetic particles with strong uniaxial effective anisotropy. We derive the dynamical susceptibility of the system on the basis of an independent-grain model by using a rectangular approach. Numerical simulations give typical line shapes depending on the anisotropy, the gyromagnetic ratio, and the damping constant. HF-FMR experiments have been performed on two systems of ultrafine cobalt particles of different sizes with a mean number of atoms per particles of 150 +/- 20 and 310 +/- 20. In both systems, the magnetic anisotropy is found to be enhanced compared to the bulk value, and increases as the particle size decreases, in accordance with previous determinations from magnetization measurements. Although no size effect has been observed on the gyromagnetic ratio, the transverse relaxation time is two orders of magnitude smaller than the bulk value indicating strong damping effects, possibly originating from surface spin disorders.

Measurement and analysis of microwave frequency response of semiconductor optical amplifiers - art. no. 682406

The measurement and analysis of the microwave frequency response of semiconductor optical amplifiers (SOAs) are proposed in this paper. The response is measured using a vector network analyzer. Then with the direct-subtracting method, which is based on the definition of scattering parameters of optoelectronic devices, the responses of both the optical signal source and the photodetector are eliminated, and the response of only the SOA is extracted. Some characteristics of the responses can be observed: the responses are quasi-highpass; the gain increases with the bias current; and the response becomes more gradient while the bias current is increasing. The multisectional model of an SOA is then used to analyze the response theoretically. By deducing from the carrier rate equation of one section under the steady state and the small-signal state, the expression of the frequency response is obtained. Then by iterating the expression, the response of the whole SOA is simulated. The simulated results are in good agreement with the measured on the three main characteristics, which are also explained by the deduced results. This proves the validity of the theoretical analysis.

Widely Frequency-Tunable Optical Microwave Source Based on Amplified Feedback Laser

A monolithic integrated amplified feedback semiconductor laser is demonstrated as an optical microwave source. The optical microwave frequency is continuously tunable in the range of 19.87-26.3 GHz with extinction ratio above 6 dB, 3-dB linewidth about 3MHz.

A 5.6-mW Power Dissipation CMOS Frequency Synthesizer for L1/L2 Dual-Band GPS Application

This paper presents a wide tuning range CMOS frequency synthesizer for dual-band GPS receiver, which has been fabricated in a standard 0.18-um RF CMOS process. With a high Q on-chip inductor, the wide-band VCO shows a tuning range from 2 to 3.6GHz to cover 2.45GHz and 3.14GHz in case of process corner or temperature variation, with a current consumption varying accordingly from 0.8mA to 0.4mA, from a 1.8V supply voltage. The measurement results show that the whole frequency synthesizer costs a very low power consumption of 5.6mW working at L I band with in-band phase noise less than -82dBc/Hz and out-of-band phase noise about -112 dBc/Hz at 1MHz offset from a 3.142GHz carrier.

A Compact Direct Digital Frequency Synthesizer for System-on-chip

A compact direct digital frequency synthesizer (DDFS) for system-on-chip (SoC) is developed in this paper. For smaller chip size and lower power consumption, the phase to sine mapping data is compressed by using sine symmetry technique, sine-phase difference technique, quad line approximation (QLA) technique and quantization and error read only memory (QE-ROM) technique. The ROM size is reduced by 98 % using the techniques mentioned above. A compact DDFS chip with 32-bit phase storage depth and a 10-bit on-chip digital to analog converter(DAC) has been successfully implemented using standard 0.35um CMOS process. The core area of the DDFS is 1.6mm(2). It consumes 167 mW at 3.3V, and its spurious free dynamic range (SFDR) is 61dB.

A Fast-Locking Phase-Locked Loop Using a Seven-State Phase Frequency Detector

A seven-state phase frequency detector (S.S PFD) is proposed for fast-locking charge pump based phase-locked loops (CPPLLs) in this paper. The locking time of the PLL can be significantly reduced by using the seven-state PFD to inject more current into the loop filter. In this stage, the bandwidth of the PLL is increased or decreased to track the phase difference of the reference signal and the feedback signal. The proposed architecture is realized in a standard 0.35 mu m 2P4M CMOS process with a 3.3V supply voltage. The locking time of the proposed PLL is 1.102 mu s compared with the 2.347 mu s of the PLL based on continuous-time PFD and the 3.298 mu s of the PLL based on the pass-transistor tri-state PFD. There are 53.05% and 66.59% reductions of the locking time. The simulation results and the comparison with other PLLs demonstrate that the proposed seven-state PFD is effective to reduce locking time.

A new frequency offset estimation for OFDM-based systems

A new carrier frequency offset estimation scheme in orthogonal frequency division multiplexing (OFDM) is proposed. The scheme includes coarse frequency offset estimation and fine frequency offset estimation. The coarse frequency offset estimation method we present is a improvement of Zhang's method. The estimation range of the new method is as large as the overall signal-band width. A new fine frequency offset estimation algorithm is also discussed in this paper. The new algorithm has a better performance than the Schmidl's algorithm. The system we use to calculate and simulate is based on the high rate WLAN standard adopted by the IEEE 802.11 stanidardization group. Numerical results are presented to demonstrate the performance of the proposed algorithm.

An adaptive frequency synthesizer architecture reducing reference sidebands

An adaptive phase-locked loop (PLL) frequency synthesizer architecture for reducing reference sidebands at the output of the frequency synthesizer is described. The architecture combines two tuning loops: one is the main loop for locking the PLL frequency synthesizer and operating all the time, the other one is auxiliary loop for reducing reference sidebands and operating only when the main loop is closely locked. A 1.8V 1GHz fully integrated CMOS dual-loop frequency synthesizer is designed in a 0.18um CMOS process. The suppression of the reference sidebands of the proposed frequency synthesizer is 13.8dB more than that of the general frequency synthesizer.

A direct digital frequency synthesizer with single-stage delta-sigma interpolator and current-steering DAC

This paper presents a direct digital frequency synthesizer (DDFS) with a 16-bit accumulator, a 4th-order single-stage pipelined delta-sigma interpolator and a 300MS/s 12-bit current-steering DAC based on Q(2) Random Walk switching scheme. The delta-sigma interpolator is used to reduce the phase truncation error and the ROM size. The measured spurious-free dynamic range (SFDR) is greater than 80 dB for 8-bit phase value and 12-bit sine-amplitude output. The DDFS prototype is fabricated in a 0.35um CMOS technology with core area of 1.11mm(2).

A new frequency offset estimation for OFDM-Based systems

A-new-carrier-frequency offset estimation scheme in orthogonal frequency division multiplexing (OFDM) is proposed. The scheme includes coarse frequency offset estimation and fine frequency offset estimation. The coarse frequency offset estimation method we present is a improvement of Zhang's method. The estimation range of the new method is as large as the overall signal-band width. A new fine frequency offset estimation algorithm is also discussed in this paper. The new algorithm has a better performance than the Schmidt's algorithm. The system we use to calculate and simulate is based on the high rate WLAN standard adopted by the IEEE 802.11 standardization group. Numerical results are presented to demonstrate the performance of the proposed algorithm.

A novel fast lock-in phase-locked loop frequency synthesizer with direct frequency presetting circuit

This paper proposes a novel, fast lock-in, phase-locked loop (PLL) frequency synthesizer. The synthesizer includes a novel mixed-signal voltage-controlled oscillator (VCO) with a direct frequency presetting circuit. The frequency presetting circuit can greatly speed up the lock-in process by accurately the presetting oscillation frequency of the VCO. We fully integrated the synthesizer in standard 0.35 mu m, 3.3 V complementary metal-oxide-semiconductors (CMOS) process. The entire chip area is only 0.4 mm(2). The measured results demonstrate that the synthesizer can speed up the lock-in process significantly and the lock-in time is less than 10 mu s over the entire oscillation frequency range. The measured phase noise of the synthesizer is -85 dBc/Hz at 10 kHz offset. The synthesizer avoids the tradeoff between the lock-in speed and the phase noise/spurs. The synthesizer monitors the chip temperature and automatically compensates for the variation in frequency with temperature.

A direct digital frequency synthesizer with fourth-order phase domain Delta Sigma noise shaper and 12-bit current-steering DAC

This paper presents a direct digital frequency synthesizer (DDFS) with a 16-bit accumulator, a fourth-order phase domain single-stage Delta Sigma interpolator, and a 300-MS/s 12-bit current-steering DAC based on the Q(2) Random Walk switching scheme. The Delta Sigma interpolator is used to reduce the phase truncation error and the ROM size. The implemented fourth-order single-stage Delta Sigma noise shaper reduces the effective phase bits by four and reduces the ROM size by 16 times. The DDFS prototype is fabricated in a 0.35-mu m CMOS technology with active area of 1.11 mm(2) including a 12-bit DAC. The measured DDFS spurious-free dynamic range (SFDR) is greater than 78 dB using a reduced ROM with 8-bit phase, 12-bit amplitude resolution and a size of 0.09 mm(2). The total power consumption of the DDFS is 200)mW with a 3.3-V power supply.