A Fast-Locking Phase-Locked Loop Using a Seven-State Phase Frequency Detector


Autoria(s): Liu, SL; Hao, ZK; Ma, HP; Yuan, L; Shi, Y
Data(s)

2008

Resumo

A seven-state phase frequency detector (S.S PFD) is proposed for fast-locking charge pump based phase-locked loops (CPPLLs) in this paper. The locking time of the PLL can be significantly reduced by using the seven-state PFD to inject more current into the loop filter. In this stage, the bandwidth of the PLL is increased or decreased to track the phase difference of the reference signal and the feedback signal. The proposed architecture is realized in a standard 0.35 mu m 2P4M CMOS process with a 3.3V supply voltage. The locking time of the proposed PLL is 1.102 mu s compared with the 2.347 mu s of the PLL based on continuous-time PFD and the 3.298 mu s of the PLL based on the pass-transistor tri-state PFD. There are 53.05% and 66.59% reductions of the locking time. The simulation results and the comparison with other PLLs demonstrate that the proposed seven-state PFD is effective to reduce locking time.

A seven-state phase frequency detector (S.S PFD) is proposed for fast-locking charge pump based phase-locked loops (CPPLLs) in this paper. The locking time of the PLL can be significantly reduced by using the seven-state PFD to inject more current into the loop filter. In this stage, the bandwidth of the PLL is increased or decreased to track the phase difference of the reference signal and the feedback signal. The proposed architecture is realized in a standard 0.35 mu m 2P4M CMOS process with a 3.3V supply voltage. The locking time of the proposed PLL is 1.102 mu s compared with the 2.347 mu s of the PLL based on continuous-time PFD and the 3.298 mu s of the PLL based on the pass-transistor tri-state PFD. There are 53.05% and 66.59% reductions of the locking time. The simulation results and the comparison with other PLLs demonstrate that the proposed seven-state PFD is effective to reduce locking time.

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IEEE Beijing Sect.; Chinese Inst Elect.; IEEE Electron Devices Soc.; IEEE EDS Beijing Chapter.; IEEE Solid State Circuits Soc.; IEEE Circuites & Syst Soc.; IEEE Hong Kong EDS, SSCS Chapter.; IEEE SSCS Beijing Chapter.; Japan Soc Appl Phys.; Elect Div IEEE.; URSI Commiss D.; Inst Elect Engineers Korea.; Assoc Asia Pacific Phys Soc.; Peking Univ, IEEE EDS Student Chapter.

[Liu, Silin; Hao, Zhikun; Ma, Heping; Yuan, Ling; Shi, Yin] Chinese Acad Sci, Inst Semicond, Beijing 100083, Peoples R China

IEEE Beijing Sect.; Chinese Inst Elect.; IEEE Electron Devices Soc.; IEEE EDS Beijing Chapter.; IEEE Solid State Circuits Soc.; IEEE Circuites & Syst Soc.; IEEE Hong Kong EDS, SSCS Chapter.; IEEE SSCS Beijing Chapter.; Japan Soc Appl Phys.; Elect Div IEEE.; URSI Commiss D.; Inst Elect Engineers Korea.; Assoc Asia Pacific Phys Soc.; Peking Univ, IEEE EDS Student Chapter.

Identificador

http://ir.semi.ac.cn/handle/172111/8300

http://www.irgrid.ac.cn/handle/1471x/65845

Idioma(s)

英语

Publicador

IEEE

345 E 47TH ST, NEW YORK, NY 10017 USA

Fonte

Liu, SL;Hao, ZK;Ma, HP;Yuan, L;Shi, Y.A Fast-Locking Phase-Locked Loop Using a Seven-State Phase Frequency Detector .见:IEEE .2008 9TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED-CIRCUIT TECHNOLOGY,345 E 47TH ST, NEW YORK, NY 10017 USA ,2008,VOLS 1-4: 1996-1999

Palavras-Chave #微电子学 #PLL
Tipo

会议论文