JFET SOS devices: Processing and gamma radiation effects

A process for fabricating n channel JFET/SOS (junction field-effect transistors on silicon-on-sapphire) has been researched. The gate p(+)n junction was obtained by diffusion, and the conductive channel was gotten by a double ion implantation. Both enhancement and depletion mode transistors were fabricated in different processing conditions. From the results of the Co-50 gamma ray irradiation experimental we found that the devices had a good total dose radiation-hardness. When the tot;ll dose was 5Mrad(Si), their threshold voltages shift was less than 0.1V. The variation of transconductance and the channel leakage current were also little.

Improvement of CMOS SOS devices characteristics by a modified solid phase epitaxy

CMOS/SOS devices have lower carriers mobility and higher channel leakage current than bulk silicon CMOS devices. These mainly results from the defects of heteroepitaxial silicon film, especially from the defects near Si-Sapphire interface. This paper describes the experiment results of CMOS/SOS devices characteristics improved by a better epitaxial silicon quality which is obtained by a modified solid phase epitaxy.

Dependence of ultra-thin gate oxide reliability on surface cleaning approach

In this paper, we investigate the effect of silicon surface cleaning prior to oxidation on the reliability of ultra-thin oxides. It is demonstrated that chemical preoxide grown in H2SO4/H2O2 (SPM) solution prior to oxidation provides better oxide integrity than both HF-based solution dipping and preoxide grown in RCA SC1 or SC2 solutions. It is also found that the oxides with SPM preoxide exhibit better hot-carrier immunity than the RCA cleaned oxides.

A new half-flash architecture for high speed video ADC

In this paper a new half-flash architecture for high speed video ADC is presented. Based on a high speed single-way analog switch circuit, this architecture effectively reduces the number of elements. At the same lime no sacrifice of speed is needed compared with the normal half-flash structure.

The design of cascaded resistors in a new analog switch two-step ADC architecture

In this paper we introduce a new Half-flash analog switch ADC architecture. And we discuss two methods to design the values of the cascaded resistors which generate the reference voltages. Derailed analysis about the effect of analog switches and comparators on reference voltages, and the methods to set the resistor values and correspond;ng voltage errors are given.

An analysis of the performance of a new high-speed single-way analog switch

This paper introduces a new highspeed single-way analog switch which has both highspeed high-resolution mono-direction analog transmission gate function and high-speed digital logic gate function with normal bipolar technology. The analysis of static and transient switching performances as an analog transmission gate is emphasized in the paper. In order to reduce the plug-in effect on high-speed high-resolution systems, an optimum design scheme is also given. This scheme is to achieve accelerated dynamic response with very low bias power dissipation. The analysis of PSPICE simulation as well as the circuit test results confirms the feasibility of the scheme. Now, the circuit has been applied effectively to the designs of novel highspeed A/D and D/A converters.

A one-way MOS analog switch

In this paper, a one-way NMOS analog switch featuring a low plug-in consumption is presented. The performances of analog switch, especially the performances of source follower are simulated under different conditions with PSPICE. Simulation results and factors affecting the deviation between input and output are analyzed, some advice on how to reduce the deviation between input and output is given. Ar the end of the paper, voltage relationship between input and output of the analog switch is obtained. Function of first degree, Vout = kVin + V0, is used to approximate the voltage relationship. The simulation results anti the value achieved from the approximation equation are given as well.

Structural and optical changes in GaAs/InAs/GaAs structure induced by thermal annealing

Self-organized InAs quantum; dots sheets are grown on GaAs(100) substrate and tapped by 80nm GaAs layer with molecular beam epitaxy. Samples were annealed and characterized with Raman spectra, transmission electron microscopy (TEM) and photolumincscence (PL). The Raman spectra indicates arsenic clusters in the GaAs capping layer. The TEM analysis revealed the relaxation of strain in some InAs islands with the introduction of the network of 90 dislocations. In addition, the structural changes also lead to the changes of the PL spectra from me InAs islands. Their correlation was discussed, Our results suggest:est that annealing may be used to intentionally modify me properties of self-organized InAs islands on GaAs.

Iron related emission spectra in InP

This paper presents a detailed PL study of Fe2+ related four zero-phonon(ZP) lines and their related phonon sidebands. Four zero-phonon transitions at approximate to 2800 cm(-1) along with the accompanying phonon sidebands extending down to 2400 cm(-1). There are ta two prominent regions in the phonon sidebands. One is ascribed to coupling to acoustic-type phonons (2700 cm(-1) region), the other is due to coupling to optic-type phonons (2500 cm(-1) region). Beside broad coupling with lattice modes, there are several groups of lines. They are ascribed to resonant modes, impurities induced gap modes and local modes.

Room-temperature continuous-wave lasing from InAs GaAs quantum dot laser grown by molecular beam epitaxy

Quantum dot lasers are predicted to have proved lasing characteristics compared to quantum well and quantum wire lasers. We report on quantum dot lasers with active media of vertically stacked InAs quantum dots layers grown by molecular beam epitaxy. The laser diodes were fabricated and the threshold current density of 220 A/cm(2) was achieved at room temperature with lasing wavelength of 951 nm. The characteristic temperature To was measured to be 333K and 157K for the temperature range of 40-180K and 180-300K, respectively.

Semi-insulating GaAs grown in outer space

A semi-insulating GaAs single crystal ingot was grown in a recoverable satellite, within a specially designed pyrolytic boron nitride crucible, in a power-traveling furnace under microgravity. The characteristics of a compound semiconductor single crystal depends fundamentally on its stoichiometry, i.e. the ration of two types of atoms in the crystal. a practical technique for nondestructive and quantitative measuring stoichiometry in GaAs single crystal was used to analyze the space-grown GaAs single crystal. The distribution of stoichiometry in a GaAs wafer was measured for the first time. The electrical, optical and structural properties of the space-grown GaAs crystal were studied systematically, Device fabricating experiments prove that the quality of field effect transistors fabricated from direct ion-implantation in semi-insulating GaAs wafers has a close correlation with the crystal's stoichiometry. (C) 2000 Elsevier Science S.A. All rights reserved.

硅条探测器前端ASIC芯片测试系统电路设计

介绍一种前端读出专用集成电路(ASIC,Application-Specific Integrated Circuit)芯片性能测试系统的电路设计与实现。该ASIC芯片可用于构成硅微条探测器、硅条、Si(Li)和CsI探测器的前端读出电子学系统。本文详细描述了测试系统的构成,主要电路设计,系统应用以及部分测试结果,并简要介绍了被测ASIC芯片的电路结构。

A low noise charge sensitive preamplifier with switch control feedback resistance

In this paper, the design and analysis of a new low noise charge sensitive preamplifier for silicon strip, Si(Li), CdZnTe and CsI detectors etc. with switch control feedback resistance were described, the entire system to be built using the CMOS transistors. The circuit configuration of the CSP proposed in this paper can be adopted to develop CMOS-based Application Specific Integrated Circuit further for Front End Electronics of read-out system of nuclear physics, particle physics and astrophysics research, etc. This work is an implemented design that we succeed after a simulation to obtain a rise time less than 3ns, the output resistance less than 94 Omega and the linearity almost good.

A Monolithic Integrated Logic Circuit of Resonant Tunneling Diodes and a HEMT

A technology for the monolithic integration of resonant tunneling diodes (RTDs) and high electron mobility transistors (HEMTs) is developed. Molecular beam epitaxy is used to grow an RTD on a HEMT structure on GaAs substrate. The RTD has a room temperature peak-to-valley ratio of 5.2:1 with a peak current density of 22.5kA/cm~2. The HEMT has a 1μm gate length with a-1V threshold voltage. A logic circuit called a monostableto-bistable transition logic element (MOBILE) circuit is developed. The experimental result confirms that the fabricated logic circuit operates successfully with frequency operations of up to 2GHz.

A GaN photodetector integrated structure for wavelength characterization of ultraviolet light

An interesting GaN photodetector structure, which can be used for characterizing the wavelength of incident ultraviolet light, is proposed. It is composed of two back-to-back integrated diodes, i.e. p-n and p-i-n GaN ultraviolet photodiodes with different spectral response. The wavelength of monochromatic ultraviolet light could be identified by measuring the photocurrent ratio value through a simple electronic circuit.