116 resultados para ASHRAE Standard 55


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In this work, a novel light source of strained InGaAsP/InGaAsP MQW EAM monolithically integrated with DFB laser is fabricated by ultra-low-pressure (22 x 10(2) Pa) selective area growth ( SAG) MOCVD technique. Superior device performances have been obtained, sue h as low threshold current of 19 mA, output light power of about 7 mW, and over 16 dB extinction ratio at 5 V applied voltage when coupled into a single mode fiber. Over 10 GHz 3 dB bandwidth in EAM part is developed with a driving voltage of 3 V. After the chip is packaged into a 7-pin butterfly compact module, 10-Gb/s NRZ transmission experiments are successfully performed in standard fiber. A clearly-open eye diagram is achieved in the module output with over 8.3 dB dynamic extinction ratio. Power penalty less than 1.5 dB has been obtained after transmission through 53.3 km of standard fiber, which demonstrates that high-speed, low chirp EAM/DFB integrated light source can be obtained by ultra-low-pressure (22 x 102 Pa) SAG method.

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A new type of self-aligned spotsize converter (SSC) integrated 1.55 mum DFB lasers had been proposed in this article. The upper optical confinement layer and the butt-coupled tapered thickness waveguide were regrown simultaneously, which not only offered the separate optimization of the active region and the integrated SSC, but also reduced the difficulty of the butt-joint selective regrowth. The vertical and horizontal far field angles were 9degrees and 12degrees respectively, the 1- dB misalignment tolerance were both 3.6 and 3.4 mum. The directed coupling efficiency to tapered single mode fiber was 48%.

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Self-assembled InAs nanostructures on (0 0 1)InP substrate have been grown by molecular beam epitaxy (MBE) and evaluated by transmission electron microscopy (TEM) and photoluminescence (PL). It is found that the morphologies of InAs nanostructures depend strongly on the underlying alloy. Through introducing a lattice-matched underlying InAlGaAs layer on InAlAs buffer layer, the InAs quantum dots (QDs) can be much more uniform in size and great improvement in PL properties can be attained at the same time. In particular, 1.55 mu m luminescence at room temperature (RT) can be realized in InAs QDs deposited on (0 0 1)InP substrate with underlying InAlGaAs layer. (C) 2000 Published by Elsevier Science B.V. All rights reserved.

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于G批量导入至Hzhangdi

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A monolithic silicon CMOS optoelectronic integrated circuit (OEIC) is designed and fabricated with standard 0.35 mu m CMOS technology. This OEIC circuit consists of light emitting diodes (LED), silicon dioxide waveguide, photodiodes and receiver circuit. The silicon LED operates in reverse breakdown mode and can be turned on at 8.5V 10mA. The silicon dioxide waveguide is composed of multiple layers of silicon dioxide between different metals layers. A two PN-junctions photodetector composed of n-well/p-substrate junction and p(+) active implantation/n-well junction maximizes the depletion region width. The readout circuitry in pixels is exploited to handle as small as 0.1nA photocurrent. Simulation and testing results show that the optical emissions powers are about two orders higher than the low frequency detectivity of silicon CMOS photodetcctor and receiver circuit.

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In this paper, a low-power, highly linear, integrated, active-RC filter exhibiting a multi-standard (IEEE 802.11a/b/g and DVB-H) application and bandwidth (3MHz, 4MHz, 9.5MHz) is present. The filter exploits digitally-controlled polysilicon resister banks and an accurate automatic tuning scheme to account for process and temperature variations. The automatic frequency calibration scheme provides better than 3% corner frequency accuracy. The Butterworth filter is design for receiver (WLAN and DVB-H mode) and transmitter (WLAN mode). The filter dissipation is 3.4 mA in RX mode and 2.3 mA (only for one path) in TX mode from 2.85-V supply. The dissipation of calibration consumes 2mA. The circuit has been fabricated in a 0.35um 47-GHz SiGe BiCMOS technology, the receiver and transmitter occupy 0.28-mm(2) and 0.16-mm(2) (calibration circuit excluded), respectively.

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This paper proposes an embedded ultra low power nonvolatile memory in a standard CMOS logic process. The memory adopts a bit cell based on the differential floating gate PMOS structure and a novel operating scheme. It can greatly improve the endurance and retention characteristic and make the area/bit smaller. A new high efficiency all-PMOS charge pump is designed to reduce the power consumption and to increase the power efficiency. It eliminates the body effect and can generate higher output voltage than conventional structures for a same stage number. A 32-bit prototype chip is fabricated in a 0.18 mu m 1P4M standard CMOS logic process and the core area is 0.06 mm(2). The measured results indicate that the typical write/erase time is 10ms. With a 700 kHz clock frequency, power consumption of the whole memory is 2.3 mu A for program and 1.2 mu A for read at a 1.6V power supply.

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A monolithic silicon CMOS optoelectronic integrated circuit (OEIC) was designed and fabricated with standard 0.6 mu m CMOS technology. This OEIC circuit consisted of an integrated double photodiode detector (DPD) and a preamplifier. The DPD detector exhibited high bandwidth by screening the bulk-generated diffusion carriers and suppressing the slow diffusion tail effect. The preamplifier exploited the regulated cascode (RGC) configuration as the input stage of receiver, thus isolating the influence of photodiode capacitance and input parasitic capacitance on bandwidth. Testing results showed that the bandwidth of OEIC was 700MHz, indicating the bit rate of 1Gb/s was achieved.

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A 1GHz monolithic photo-detector (PD) and trans-impedance amplifier (TIA) is designed with the standard 0.35 mu m CMOS technique. The design of the photo-detector is analyzed and the CMOS trans-impedance amplifier is also analyzed in the paper. The integrating method is described too. The die photograph is also showed in the paper.

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Self-assembly Ge quantum dots (QD) on Si and Si/Ge mutli-quantum-wells (MQW) are grown by MBE. The island size and island density was investigated by atomics force microscopy. Ten-layer and twenty-layer MQW were selected for photodiode device fabrication. In photoluminescence (PL), a broad peak around 1.55-mu m wavelength was observed with higher peak intensity for the 10-layer MQW which had less defects than the 20-layer sample. Resonant cavity enhanced (RCE) photodiodes were fabricated by bonding on a SOI wafer. Selected responsivity at 1.55 mu m was successfully demonstrated. (c) 2005 Elsevier B.V. All rights reserved.

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A silicon light emitting device is designed and simulated. It is fabricated in 0.6 mum standard CMOS technology. The device can give more than 1 muW optical power of visible light under reverse breakdown. The device can be turned on at a bias of 0.88 V and work in a large range of voltage: 1.0-6.0 V The external electrical-optical conversion efficiency is more than 10(-6). The optical spectrum of the device is between 540-650 nm, which have a clear peak near 580 nm. The emission mechanism can be explained by a hot carrier direct recombination model.

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The high quality Ge islands material with 1.55 mu m photo-response grown on Sol substrate is reported. Due to the modulation of the cavity formed by the mirrors at the surface and the buried SiO2 interface, seven sharp and strong peaks with narrow linewidth are found. And a 1.55 mu m Ge islands resonant-cavity-enhanced (RCE) detector with narrowband was fabricated by a simple method. The bottom mirror was deposited in the hole formed by anisotropically etching, in a basic solution from the backside of the sample with the buried SiO2 layer in silicon-on-insulator substrate as the etch-stop layer. Reflectivity spectrum indicates that the mirror deposited in the hole has a reflectivity as high as 99% in the range of 1.2-1.65 mu m. The peak responsivity of the RCE detector at 1543.8 nm is 0.028 mA/W and a full width at half maximum of 5 nm is obtained. Compared with the conventional p-i-n photodetector, the responsivity of RCE detector has a nearly threefold enhancement.

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An ultra low power non-volatile memory is designed in a standard CMOS process for passive RFID tags. The memory can operate in a new low power operating scheme under a wide supply voltage and clock frequency range. In the charge pump circuit the threshold voltage effect of the switch transistor is almost eliminated and the pumping efficiency of the circuit is improved. An ultra low power 192-bit memory with a register array is implemented in a 0.18 mu M standard CMOS process. The measured results indicate that, for the supply voltage of 1.2 volts and the clock frequency of 780KHz, the current consumption of the memory is 1.8 mu A (3.6 mu A) at the read (write) rate of 1.3Mb/s (0.8Kb/s).

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We report the experimental result of all-optical passive 3.55 Gbit/s non-return-to-zero (NRZ) to pseudo-return-to-zero (PRZ) format conversion using a high-quality-factor (Q-factor) silicon-based microring resonator notch filter on chip. The silicon-based microring resonator has 23800 Q-factor and 22 dB extinction ratio (ER), and the PRZ signals has about 108 ps width and 4.98 dB ER.

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The use of alpha-power chirped fiber Bragg gratings for dispersion cancellation in an optical fiber link is discussed. Numerical and theoretical investigation of recompressing the dispersion-broadened pulse by using alpha-power chirped gratings is made, which shows that, the dispersion-broadened Gaussian pulse after 100 km standard fiber (with zero dispersion at lambda = 1.3 mu m) trnasmission at lambda = 1.55 mu m with initial width of T-FWHM = 33ps (full width at half maximum) can be perfectly recompressed with the peak reflectivity of 82% by using a 30 mm long alpha-power chirped fiber grating with proper a value and optimal grating parameters.