An Ultra Low Power Non-volatile Memory in Standard CMOS Process for Passive RFID Tags

An ultra low power non-volatile memory is designed in a standard CMOS process for passive RFID tags. The memory can operate in a new low power operating scheme under a wide supply voltage and clock frequency range. In the charge pump circuit the threshold voltage effect of the switch transistor is almost eliminated and the pumping efficiency of the circuit is improved. An ultra low power 192-bit memory with a register array is implemented in a 0.18 mu M standard CMOS process. The measured results indicate that, for the supply voltage of 1.2 volts and the clock frequency of 780KHz, the current consumption of the memory is 1.8 mu A (3.6 mu A) at the read (write) rate of 1.3Mb/s (0.8Kb/s).

Submitted by 阎军 (yanj@red.semi.ac.cn) on 2010-04-13T02:52:44Z No. of bitstreams: 1 An Ultra Low Power Non-volatile Memory in Standard CMOS Process for Passive RFID Tags.pdf: 874458 bytes, checksum: c80e61879ac7b936ab6377a6d24600eb (MD5)

Made available in DSpace on 2010-04-13T02:52:44Z (GMT). No. of bitstreams: 1 An Ultra Low Power Non-volatile Memory in Standard CMOS Process for Passive RFID Tags.pdf: 874458 bytes, checksum: c80e61879ac7b936ab6377a6d24600eb (MD5) Previous issue date: 2009

IEEE Solid State Circuits Soc.; IEEE Electron Decices Soc.

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IEEE Solid State Circuits Soc.; IEEE Electron Decices Soc.