A widely tunable continuous-time LPF for a direct conversion DBS Tuner

A continuous-time 7th-order Butterworth Gm-C low pass filter (LPF) with on-chip automatic tuning circuit has been implemented for a direct conversion DBS tuner in a 0.35um SiGe BiCMOS technology. The filter's -3dB cutoff frequency f(0) can be tuned from 4MHz to 40MHz. A novel translinear transconductor (Gm) cell is used to implement the widely tunable and high linear filter. The filter has -0.5dB passband gain, 28nV/Hz(1/2) input referred noise, -2dBVrms passband IIP3, 24dBVrms stopband IIP3. The I/Q LPFs with the tuning circuit draw 16mA (with f(0)=20MHz) from 3.3 V supply, and occupy an area of 0.45 mm(2).

Neuro-Stimulus Chip with Photodiodes Array for Sub-retinal Implants

A prototype neuro-stimulus chip for sub-retinal implants in blind patients affected by Age-related Macular Degeneration (AMD) or Retinitis Pigmentosa (RP) is presented in this paper. This retinal prosthetic chip was designed to replace the degenerated photoreceptor cells, and in order to stimulate directly the remaining healthy layers of retinal neurons. The current stimulus circuits are monolithic integrated with photodiodes (PD) array, which can convert the illumination on the eyes into bi-phasic electrical pulses. In addition, a novel charge cancellation circuit is used to discharge the electrodes for medical safty. The prototype chip is designed and fabricated in HJTC 0.18 mu m N-well CMOS 1P6M Mix-signal process, with a +/- 2.5 V dual voltage power supply.

A Compact Direct Digital Frequency Synthesizer for System-on-chip

A compact direct digital frequency synthesizer (DDFS) for system-on-chip (SoC) is developed in this paper. For smaller chip size and lower power consumption, the phase to sine mapping data is compressed by using sine symmetry technique, sine-phase difference technique, quad line approximation (QLA) technique and quantization and error read only memory (QE-ROM) technique. The ROM size is reduced by 98 % using the techniques mentioned above. A compact DDFS chip with 32-bit phase storage depth and a 10-bit on-chip digital to analog converter(DAC) has been successfully implemented using standard 0.35um CMOS process. The core area of the DDFS is 1.6mm(2). It consumes 167 mW at 3.3V, and its spurious free dynamic range (SFDR) is 61dB.

A Fast-Locking Phase-Locked Loop Using a Seven-State Phase Frequency Detector

A seven-state phase frequency detector (S.S PFD) is proposed for fast-locking charge pump based phase-locked loops (CPPLLs) in this paper. The locking time of the PLL can be significantly reduced by using the seven-state PFD to inject more current into the loop filter. In this stage, the bandwidth of the PLL is increased or decreased to track the phase difference of the reference signal and the feedback signal. The proposed architecture is realized in a standard 0.35 mu m 2P4M CMOS process with a 3.3V supply voltage. The locking time of the proposed PLL is 1.102 mu s compared with the 2.347 mu s of the PLL based on continuous-time PFD and the 3.298 mu s of the PLL based on the pass-transistor tri-state PFD. There are 53.05% and 66.59% reductions of the locking time. The simulation results and the comparison with other PLLs demonstrate that the proposed seven-state PFD is effective to reduce locking time.

A Synthesis Tool for a Tile-Based Heterogeneous FPGA

A multi-mode logic cell architecture in a tile-based heterogeneous FPGA is proposed, and a logic synthesis tool, called Vsyn, based on this architecture is presented. The logic cell architecture design and its synthesis tool development are strongly influencing each other. Any feature or parameter from one needs to be fully exercised and verified on the other. In this paper, we presented experimental results based MCNC benchmarks to show that the integration of the synthesis tool and the FPGA architecture can achieve high performance in the targeted FPGA applications. In addition, Vsyn can also target embedded special-purpose macros for the heterogeneous FPGA.

In-situ Boron-doped Low-stress LPCVD Polysilicon for Micromechanical Disk Resonator

Polycrystalline silicon (polysilicon) has been used as an important structural material for microelectro-mechnical systems (MEMS) because of its compatibility with standard integrated circuit (IC) processes. As the structural layer of micromechanical high resonance frequency (high-f) and high quality factor (high-Q) disk resonators, the low residual stress and low resistivity are desired for the polysilicon thin films. In the present work, we investigate the effect of deposition and annealing conditions on the residual stress and resistivity for in-situ deposited low pressure chemical vapor deposition (LPCVD) polysilicon films. Low residual stress (-100 MPa) was achieved in in-situ boron-doped polysilicon films deposited at 570 degrees C and annealed at 1000 degrees C for 4 hr. The as-deposited amorphous polysilicon films were crystallized by the rapid thermal annealing and have the (111)-preferred orientation, the low tensile residual stress is expected for this annealed film, the detailed description on this work will be reported soon. The controllable residual stress and resistivity make these films suitable for high-Q and bigh-f micro-mechanical disk resonators.

Simulation and fabrication of the SiC-based clamped-clamped filter

In this paper, the SiC-based clamped-clamped filter was designed and fabricated. The filter was composed of two clamped-clamped beam micromechanical resonators coupled by a spring coupling beam. Structural geometries, including the length and width of the resonator beam and coupling beam, were optimized by simulation for high frequency and high Q, under the material properties of SiC. The vibrating modes for the designed filter structure were analyzed by finite element analysis (FEA) method. For the optimized structure, the geometries of resonator beams and coupling beams, as well as the coupling position, the SiC-based clamped-clamped filter was fabricated by surface micromaching technology.

An 8-b 1-GSmaples/s CMOS cascaded folding and interpolating ADC

This paper presents an 8-bit low power cascaded folding and interpolating analog-to-digital converter (ADC). A reduction in the number of comparators, equal to the number of times the signal is folded, is obtained. The interleaved architecture is used to improve the sampling rate of the ADC. The circuit including a bandgap is implemented in a 0.18-mu m CMOS technology, and measures 1.47 mm X 1.47 mm (including pads). The simulation results illustrate a conversion rate of 1-GSamples/s and a power dissipation of less than 290mW.

A 1Gb/s silicon photo-receiver in standard CMOS for 850-nm optical communication

A monolithic silicon CMOS optoelectronic integrated circuit (OEIC) was designed and fabricated with standard 0.6 mu m CMOS technology. This OEIC circuit consisted of an integrated double photodiode detector (DPD) and a preamplifier. The DPD detector exhibited high bandwidth by screening the bulk-generated diffusion carriers and suppressing the slow diffusion tail effect. The preamplifier exploited the regulated cascode (RGC) configuration as the input stage of receiver, thus isolating the influence of photodiode capacitance and input parasitic capacitance on bandwidth. Testing results showed that the bandwidth of OEIC was 700MHz, indicating the bit rate of 1Gb/s was achieved.

Quantum well infrared photodetector simultaneously working in two atmospheric windows

We have demonstrated a two-contact quantum well infrared photodetector (QWIP) exhibiting simultaneous photoresponse in both the mid- and the long-wavelength atmospheric windows of 3-5 mu m and of 8-12 mu m. The structure of the device was achieved by sequentially growing a mid-wavelength QWIP part followed by a long-wavelength QWIP part separated by an n-doped layer. Compared with the conventional dual-band QWIP device utilizing three ohmic contacts, our QWIP is promising to greatly facilitate two-color focal plane array (FPA) fabrication by reducing the number of the indium bumps per pixel from three to one just like a monochromatic FPA fabrication and to increase the FPA fill factor by reducing one contact per pixel; another advantage may be that this QWIP FPA boasts broadband detection capability in the two atmospheric windows while using only a monochromatic readout integrated circuit. We attributed this simultaneous broadband detection to the different distributions of the total bias voltage between the mid- and long-wavelength QWIP parts.

Ti Schottky barrier diodes on n-type 6H-SiC

Using thermal evaporation, Ti/6H-SiC Schottky barrier diodes (SBD) were fabricated. They showed good rectification characteristics from room temperature to 200degreesC. At low current density. the current conduction mechanism follows the thermionic emission theory. These diodes demonstrated a low reverse leakage current of below 1 X 10(-4)Acm(-2). Using neon implantation to form the edge termination, the breakdown voltage was improved to be 800V. In addition. these SBDs showed superior switching characteristics.

A semiconductor laser suitably fabricated by planar technology

The semiconductor microlasers with an equilateral triangle resonator which can be fabricated by dry etching technique from the laser wafer of the edge emitting laser, are analyzed by FDTD technique and rate equations. The results show that ETR microlaser is suitable to realize single mode operation. By connecting an output waveguide to one of the vertices of the ETR, we still can get the confined modes with high quality factors. The EM microlasers are potential light sources for photonic integrated circuits.

Hybrid CMOS/VCSEL optoelectronic modules

We report some investigations on vertical cavity surface emitting laser (VCSEL) arrays and VCSEL based optoelectronic smart photonic multiple chip modules (MCM), consisting of 1x16 vertical cavity surface emitting laser array and 16-channel lasers driver 0.35 Pin CMOS circuit. The hybrid integrated multiple chip modules based on VCSEL operate at more than 2GHz in -3dB frequency bandwidth.

Observation of deep electron states in n-type Al-doped ZnS1-xTex grown by molecular beam epitaxy

Deep level transient spectroscopy (DLTS) technique was used to investigate deep electron states in n-type Al-doped ZnS1-xTex epilayers grown by molecular fiction epitaxy (MBE), Deep level transient Fourier spectroscopy (DLTFS) spectra of the Al-doped ZnS1-xTex (x = 0. 0.017, 0.04 and 0.046. respectively) epilayers reveal that At doping leads to the formation of two electron traps at 0.21 and 0.39 eV below the conduction hand. 1)DLTFS results suggest that in addition to the rules of Te as a component of [lie alloy as well as isoelectronic centers, Te is also involved in the formation of all electron trip, whose energy level relative to the conduction hand decreases a, Te composition increases.

Artificial neural networks expecting more advanced microelectronics technology