1-Gb/s zero-pole cancellation CMOS transimpedance amplifier for Gigabit Ethernet applications

A zero-pole cancellation transimpedance amplifier (TIA) has been realized in 0.35 μm RF CMOS tech nology for Gigabit Ethernet applications. The TIA exploits a zero-pole cancellation configuration to isolate the input parasitic capacitance including photodiode capacitance from bandwidth deterioration. Simulation results show that the proposed TIA has a bandwidth of 1.9 GHz and a transimpedance gain of 65 dB·Ω for 1.5 pF photodiode capaci tance, with a gain-bandwidth product of 3.4 THz·Ω. Even with 2 pF photodiode capacitance, the bandwidth exhibits a decline of only 300 MHz, confirming the mechanism of the zero-pole cancellation configuration. The input resis tance is 50 Ω, and the average input noise current spectral density is 9.7 pA/(Hz)~(1/2). Testing results shows that the eye diagram at 1 Gb/s is wide open. The chip dissipates 17 mW under a single 3.3 V supply.

A multi-standard active-RC filter with accurate tuning system

A low-power, highly linear, multi-standard, active-RC filter with an accurate and novel tuning architec-ture is presented. It exhibits 1EEE 802. 11a/b/g (9.5 MHz) and DVB-H (3 MHz, 4 MHz) application. The filter exploits digitally-controlled polysilicon resistor banks and a phase lock loop type automatic tuning system. The novel and complex automatic frequency calibration scheme provides better than 4 comer frequency accuracy, and it can be powered down after calibration to save power and avoid digital signal interference. The filter achieves OIP3 of 26 dBm and the measured group delay variation of the receiver filter is 50 ns (WLAN mode). Its dissipation is 3.4 mA in RX mode and 2.3 mA (only for one path) in TX mode from a 2.85 V supply. The dissipation of calibration consumes 2 mA. The circuit has been fabricated in a 0.35μm 47 GHz SiGe BiCMOS technology; the receiver and transmitter filter occupy 0.21 mm~2 and 0.11 mm~2 (calibration circuit excluded), respectively.

A high speed direct digital frequency synthesizer realized by a segmented nonlinear DAC

This paper presents a high speed ROM-less direct digital frequency synthesizer (DDFS) which has a phase resolution of 32 bits and a magnitude resolution of 10 bits. A 10-bit nonlinear segmented DAC is used in place of the ROM look-up table for phase-to-sine amplitude conversion and the linear DAC in a conventional DDFS.The design procedure for implementing the nonlinear DAC is presented. To ensure high speed, current mode logic (CML) is used. The chip is implemented in Chartered 0.35μm COMS technology with active area of 2.0 × 2.5 mm~2 and total power consumption of 400 mW at a single 3.3 V supply voltage. The maximum operating frequency is 850 MHz at room temperature and 1.0 GHz at 0 ℃.

An asymmetric MOSFET-C band-pass filter with on-chip charge pump auto-tuning

An asymmetric MOSFET-C band-pass filter(BPF)with on chip charge pump auto-tuning is presented.It is implemented in UMC (United Manufacturing Corporation)0.18μm CMOS process technology. The filter system with auto-tuning uses a master-slave technique for continuous tuning in which the charge pump OUtputs 2.663 V, much higher than the power supply voltage, to improve the linearity of the filter. The main filter with third order low-pass and second order high-pass properties is an asymmetric band-pass filter with bandwidth of 2.730-5.340 MHz. The in-band third order harmonic input intercept point(HP3) is 16.621 dBm,wim 50 Ω as the source impedance. The input referred noise iS about 47.455μVrms. The main filter dissipates 3.528 mW while the auto-tuning system dissipates 2.412 mW from a 1.8 V power supply. The filter with the auto-tuning system occupies 0.592 mm~2 and it can be utilized in GPS (global positioning system)and Bluetooth systems.

A low power high linearity baseband for a direct conversation CMMB tuner

An analog baseband circuit made in a 0.35-μm SiGe BiCMOS process is presented for China Multimedia Mobile Broadcasting (CMMB) direct conversion receivers. A high linearity 8th-order Chebyshev low pass filter (LPF) with accurate calibration system is used. Measurement results show that the filter provides 0.5-dB pass-band ripple, 4% bandwidth accuracy, and -35-dB attenuation at 6 MHz with a cutoff frequency of 4 MHz. The current steering type variable gain amplifier (VGA) achieves more than 40-dB gain range with excellent temperature compensation.This tuner baseband achieves an OIP3 of 25.5 dBm, dissipates 16.4 mA under a 2.8-V supply and occupies 1.1 mm~2 of die size.

An asymmetric broad waveguide structure for a 0.98-μm high-conversion-efficiency diode laser

A novel asymmetric broad waveguide diode laser structure was designed for high power conversion efficiency (PCE). The internal quantum efficiency, the series resistance, and the thermal resistance were theoretically optimized. The series resistance and the thermal resistance were greatly decreased by optimizing the thickness of the P-waveguide and the P-cladding layers. The internal quantum efficiency was increased by introducing a novel strain-compensated GaAs_0.9P_0.1/InGaAs quantum well. Experimentally, a single 1-cm bar with 20% fill factor and 900 μm cavity length was mounted P-side down on a microchannel-cooled heatsink, and a peak PCE of 60% is obtained at 26.3-W continuous wave output power.The results prove that this novel asymmetric waveguide structure design is an efficient approach to improve the PCE.

A 10-bit 50-MS/s sample-and-hold circuit with low distortion sampling switches

A fully-differential switched-capacitor sample-and-hold (S/H) circuit used in a 10-bit 50-MS/s pipeline analog-to-digital converter (ADC) was designed and fabricated using a 0.35-μm CMOS process. Capacitor fliparound architecture was used in the S/H circuit to lower the power consumption. In addition, a gain-boosted operational transconductance amplifier (OTA) was designed with a DC gain of 94 dB and a unit gain bandwidth of 460 MHz at a phase margin of 63 degree, which matches the S/H circuit. A novel double-side bootstrapped switch was used, improving the precision of the whole circuit. The measured results have shown that the S/H circuit reaches a spurious free dynamic range (SFDR) of 67 dB and a signal-to-noise ratio (SNR) of 62.1 dB for a 2.5 MHz input signal with 50 MS/s sampling rate. The 0.12 mm~2 S/H circuit operates from a 3.3 V supply and consumes 13.6 mW.

A widely tunable continuous-time LPF for a direct conversion DBS tuner

A continuous-time 7th-order Butterworth Gm-C low pass filter (LPF) with on-chip automatic tuning circuit has been implemented for a direct conversion DBS tuner in 0.35μm SiGe BiCMOS technology. The filter's -3 dB cutoff frequency f0 can be tuned from 4 to 40 MHz. A novel on-chip automatic tuning scheme has been successfully realized to tune and lock the filter's cutoff frequency. Measurement results show that the filter has -0.5 dB passband gain, +/- 5% bandwidth accuracy, 30 nV/Hz~(1/2) input referred noise, -3 dBVrms passband IIP3, and 27 dBVrms stopband IIP3. The I/Q LPFs with the tuning circuit draw 13 mA (with f_0 = 20 MHz) from 5 V supply, and occupy 0.5 mm~2.

A fast-settling frequency-presetting PLL frequency synthesizer with process variation compensation and spur reduction

This paper proposes a fast-settling frequency-presetting PLL frequency synthesizer. A mixed-signal VCO and a digital processor are developed to accurately preset the frequency of VCO and greatly reduce the settling time. An auxiliary tuning loop is introduced in order to reduce reference spur caused by leakage current. The digital processor can automatically compensate presetting frequency variation with process and temperature, and control the operation of the auxiliary tuning loop. A 1.2 GHz integer-N synthesizer with 1 MHz reference input Was implemented in a 0.18μm process. The measured results demonstrate that the typical settling time of the synthesizer is less than 3μs,and the phase noise is -108 dBc/Hz@1MHz.The reference spur is -52 dBc.

GaAs基MOEMS波长可调谐滤波器的设计和理论模拟

采用传输矩阵理论和结合悬臂梁的电学一机械模型对GaAs基1.55 μm微光电机械系统(MOEMS)波长可调谐滤波器的光学和电学特性进行了深入的对比分析和研究.结果表明,采用800 nm厚的空气腔可以实现滤波器波长的调谐范围为100 nm,所需最大反向偏压为4 V,波长的调谐速率可以达到1.83 MHZ.

用正电子研究原生ZnO单晶中的缺陷

利用正电子寿命谱和多普勒展宽谱技术研究了原生ZnO的缺陷结构及其退火效应. 经900 ℃退火之后,正电子寿命实验显示样品中的空位型缺陷基本被消除,其体寿命为180 ps.通过比较原生和退火样品的符合多普勒展宽谱的商谱曲线,两者有相似的峰型,结合寿命谱的相关数据表明原生ZnO中不存在H原子填充Zn空位.

Efficient Mode-locked and Q-switched Nd∶YVO_4 Laser with Semiconductor Saturable Absorber Mirror

We reported an efficient diode pumped Nd ! YVO, 1 064 nm laser passively mode-locked and Q-switched by a semiconductor saturable absorber mirror(SESAM). At the incident pump power of 7. 5 W, 2. 81 W average output power was obtained during stable CW mode locking with a repetition rate of 111 MHz. The optical conversion efficiency was 37. 5% , and the slope efficiency was 39%. So far as we know, this is the highest optical-optical conversion efficiency with a SESAM at home.

CMOS超高频整流器

提出了一个适用于无源UHF RFID标签芯片的全CMOS整流器.整流器包括射频-直流转换电路、偏置电路、直流-直流转换电路和振荡器电路.整流器的工作频率范围是860～960 MHz.基于0.18μm,1p6m的标准数字CMOS工艺,设计并实现了无源UHF RFID标签芯片的整流器.该设计采用开关电容电路技术动态地消除了CMOS管开启电压的问题,在标准数字CMOS工艺下实现了高效率的超高频整流器.整流器的面积为180μm×140μm.当输入900MHz,-16dBm的射频信号时,整流器的输出电压为1.2V,启动时间为980μs.

用于神经电信号记录的多通道微探针

以体硅为衬底，采用微机械加工技术(MEMS)制作了七通道的可植入到脑皮层的微探针，用于记录神经电信号．从生物相容性、减小植入损伤、工艺制作难度等方面考虑，制作了以二氧化硅／硅(SiO_2／Si)为主体的微探针，并详述了其具体制作工艺流程．扫描电镜(SEM)照片显示微探针针长3 mm、针宽100 μm、针厚约为20μm，各个记录点直径10μm、间距120μm，实现了各通道之间良好的信号隔离．微探针距离针尖1 mm范围内的针宽以一定弧度由100μm逐渐变窄，同时针尖锥角为6°，此种结构有利于减小植入时对脑组织的损伤．通过体外测试得到，当频率由10 kHz增加到10 MHz时，微电极各个通道阻抗由150.5 kΩ降低到6.0 kΩ．

掺Er／Pr的GaN薄膜深能级的研究

利用深能级瞬态谱（DLTS）、傅里叶变换红外光谱（FT-IR）对GaN以及GaN掺Er／Pr的样品进行了电学和光学特性分析．研究发现未掺杂的GaN样品只在导带下0．270eV处有一个深能级；GaN注入Er经900℃，30min退火后的样品出现了四个深能级，能级位置位于导带下0．300eV，0．188eV，0．600eV和0．410eV；GaN注入Pr经1050℃，30min退火后的样品同样出现了四个深能级。能级位置位于导带下0．280eV，0．190eV，0．610eV和0．390eV；对每一个深能级的来源进行了讨论．光谱研究表明，掺Er的GaN样品经900℃，30min退火后，可以观察到Er的1538nm处的发光。而且对能量输运和发光过程进行了讨论．